This U.S. non-provisional application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2023-0066576, filed on May 23, 2023, and Korean Patent Application No. 10-2023-0122763, filed on Sep. 14, 2023, in the Korean Intellectual Property Office, the disclosures of which are herein incorporated by reference in their entireties.
Semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted. A dynamic random access memory (DRAM) is a type of nonvolatile memory device and is used in various fields such as mobile systems, servers, and graphics devices.
A volatile memory device is described for allocating specific data.
An example memory device includes a bank connected to a plurality of wordlines and a plurality of column select lines (CSLs). Among the plurality of wordlines, every r-th wordline (where r is a positive integer) may be allocated for metadata in a column direction.
An example memory device includes a bank connected to a plurality of wordlines and a plurality of column select lines (CSLs), a row decoder connected to the plurality of wordlines and extending in a column direction, and a column decoder connected to the plurality of CSLs and extending in a row direction. Among the plurality of wordlines, every r-th wordline (where r is a positive integer) may be allocated for metadata in the column direction.
An example memory device includes a subbank divided in a row direction and comprising a plurality of subsets each divided in the row direction, a plurality of wordlines extending in the row direction and connected to the subbank, wherein among the plurality of wordlines, every r-th wordline (where r is a positive integer) is allocated for metadata in a column direction, and a plurality of column select line (CSL) subsets extending in the column direction and connected to the subbank.
The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings.
Hereinafter, example embodiments will be described with reference to the accompanying drawings.
Referring to
The memory controller 110 may control the overall operation of the memory system 100, and may control data exchange between the memory device 120 and a host device connected to the memory system 100. For example, the memory controller 110 may control the memory device 120 to write or read data based on a request from the host device.
The memory controller 110 may communicate with the memory device 120 through a memory interface or communicate with a host device through a host interface. Accordingly, the memory controller 110 may mediate a signal between the host device and the memory device 120. The memory controller 110 may control the memory device 120 based on a command CMD for controlling the memory device 120. For example, the memory device 120 may include a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), a DDR5 SDRAM, a DDR6 SDRAM, a low-power DDR4 (LPDDR4) SDRAM, an LPDDR5 SDRAM, an LPDDR6 SDRAM, or the like. However, example implementations are not limited thereto, and the memory device 120 may include a nonvolatile memory device. However, in an example the memory device 120 is a volatile memory.
The memory controller 110 may transmit the above-described command CMD, a clock signal CLK, and an address ADDR to the memory device 120. The memory controller 110 may provide data DQ to the memory device 120, and may rec receive data DQ from the memory device 120. The memory device 120 may include a memory cell array 130 in which data DQ is stored, a control logic circuit 140, and a data input/output buffer 150, or the like.
The memory cell array 130 may include a plurality of memory cells. Each of the memory cells may store data (for example, 1 bit). The memory cell array 130 may include a plurality of wordlines and a plurality of column select lines (CSLs), and the plurality of memory cells may be connected to each wordline and each CSL. In this case, memory cells connected to a wordline may be referred to as rows, and memory cells selected by a CSL may be referred to as columns.
A portion of the wordlines may be allocated for metadata. The metadata may be defined as data used to improve performance of the memory device 120 and to enhance security of the memory device 120. Except for a wordline WL_M allocated for the metadata, the remaining wordlines WL_N may be allocated for normal data. The normal data may be defined as data other than the metadata.
According to various embodiments, a ratio of normal data to metadata accessed by the memory device 120 may be required. For example, the required ratio of normal data and metadata accessed by the memory device 120 (hereinafter, a required normal/meta ratio) may be set to n:1 (where n is a positive integer). For example, n may be 8 or 16, but example implementations are not limited thereto. For example, in the case in which n=8, 8 bytes of metadata may be required to be accessed when 64 bytes of normal data are accessed.
One or more bitlines may be connected to a CSL. Therefore, when a single CSL is selected, for example, when a single column is selected, all of the one or more bitlines connected to the selected CSL may be selected, and data in units of burst length may be simultaneously input and output from the one or more selected bitlines. For example, eight bitlines may be connected to a single CSL, but example implementations are not limited thereto.
The control logic circuit 140 may receive a command CMD and an address ADDR from the memory controller 110. The control logic circuit 140 may control the memory cell array 130 based on the command CMD and the address ADDR. For example, the control logic circuit 140 may decode the command CMD and generate control signals corresponding to the decoded command CMD. In addition, the control logic circuit 140 may generate internal command (CMD) signals such as a refresh signal, an active signal, a precharge signal, a read signal, or a write signal. In addition, the control logic circuit 140 may decode the address ADDR and select or activate a wordline and a CSL corresponding to the decoded address ADDR.
The data input/output buffer 150 may provide normal data and/or metadata to memory cell array 130 based on a clock signal CLK when a write operation is performed, or may provide normal data and/or metadata provided from memory cell array 130 to the memory controller 110 based on a clock signal CLK when a read operation is performed.
According to various implementations, the memory system 100, the memory controller 110, and the memory device 120 included in the memory system 100 may operate in a metadata mode. The metadata mode may be an operation mode in which metadata is input or output. When operating in the metadata mode, the memory system 100 may perform a write or read operation based on the wordline WL_M allocated for metadata, according to various implementations (
For example, the memory controller 110 and the control logic circuit 140 may control the memory device 120 to simultaneously write or read normal data and metadata through a wordline WL_N allocated to the normal data and a wordline WL_M allocated to the metadata.
In an example implementation, the memory system 100 may turn off the metadata mode and operate in a normal mode. In the normal mode, the wordline WL_M that has been allocated for the metadata in the metadata mode may also be allocated for the normal data. Accordingly, in the normal mode, the memory system 100 may activate at least a portion of the plurality of wordlines included in the memory device 120 to write or read the normal data from the memory device 120. In addition, the operation of the memory system 100 in the normal mode may conform to an operation of DRAM, DDR4, SDRAM, DDR5 SDRAM, DDR6 SDRAM, LPDDR4 SDRAM, LPDDR5 SDRAM, or LPDDR6 SDRAM.
According to the above-described implementations, a portion of the wordlines connected to the memory cell array 130 included in the memory device 120 may be allocated for, for example, the metadata. For example, a portion of carved rows may be used for metadata in terms of rows. When additional registers or lines (for example, global input/output (GIO) lines, or the like) are allocated for metadata, overhead may occur due to a chip size. However, according to example implementations, a portion of existing wordlines may be allocated for metadata to reduce overhead occurring due to a chip size.
Referring to
The bank unit BU, also known as a “bank group,” may be provided in plural depending on the capacity of the memory device 120. A portion of the plurality of bank units BU and the remaining portion may be arranged in a row direction d2 with a peripheral circuit region PERI interposed therebetween. Each of the bank units BU may include a plurality of banks. Each of the plurality of banks may include a plurality of mats including a plurality of memory cells.
According to an example implementation, each of the plurality of banks may include a plurality of subbanks. The plurality of subbanks included in each of the banks may correspond to the same bank address. In the following implementations including
The row decoders RD1 and RD2 may extend in the column direction d1 and may be provided in a number corresponding to the number of banks included in a single bank unit BU. According to an example implementation, the row decoders RD1 and RD2 may select wordlines connected to subbanks included in different banks based on decoding a row address. For example, the first row decoder RD1 may select a wordline connected to the 1-1-th subbank SB1-1 and the 2-1-th subbank SB2-1, and the second row decoder RD2 may select a wordline connected to the 1-2-th subbank SB1-2 and the 2-2-th subbank SB2-2.
The column decoders CD1 and CD2 may extend in the row direction d2 and may be provided in a number corresponding to the number of banks included in a single bank unit BU. According to an example implementation, the column decoders CD1 and CD2 may select a CSL connected to a subbank included in the same bank based on decoding a column address. For example, the first column decoder CD1 may select a CSL connected to the 1-1-th subbank SB1-1 and the 2-1-th subbank SB2-1, and the second column decoder CD2 may select a CSL connected to the 1-2-th subbank SB1-2 and the 2-2-th subbank SB2-2.
Referring to
According to the example implementation of
According to an example implementation, normal data and metadata corresponding to the normal data may be simultaneously written in the first bank B1. When a read operation is performed on normal data ND and metadata MD written in the first bank B1, the normal data ND and the metadata MD may be simultaneously read through the two wordlines WL_M and WL_N by simultaneously activating two wordlines WL_M and WL_N for each subbank (each of the 1-1-th subbank SB1-1 and 1-2-th subbank SB1-2). For example, a first row decoder RD1 and a second row decoder RD2 may simultaneously select the normal data wordline WL_N and the metadata wordline WL_M, respectively. In addition, a specific CSL may be selected through a first column decoder CD1 and a second column decoder CD2.
According to an example implementation, write operations of normal data and metadata corresponding to the normal data may be simultaneously performed. When write operations of the normal data ND and the metadata MD are performed in the first bank B1, each subbank (each of the 1-1-th subbank SB1-1 and the 1-2-th subbank SB1-2), the normal data ND and the metadata MD may be simultaneously written through the two wordlines WL_M and WL_N by activating both of the wordlines WL_M and WL_N. For example, the first row decoder RD1 and the second row decoder RD2 may simultaneously select the normal data wordline WL_N and the metadata wordline WL_M, respectively. In addition, a specific CSL may be selected through the first column decoder CD1 and the second column decoder CD2.
Then, data on a selected wordline and a CSL may be read or written through a GIO line connected to each subbank. GIO may extend in a column direction d1 and be spaced apart in a row direction d2 According to an example implementation, first GIO GIO1 may be configured to be shared with the 1-1-th subbank SB1-1 of the first bank B1 and the 2-1-th subbank SB2-1 of the second bank B2, and second GIO GIO2 may be configured to be shared with the 1-2-th subbank SB1-2 of the first bank B1 and the 2-2-th subbank SB2-2 of the second bank B2. For example, subbanks belonging to different banks may be configured to share the same GIO. Subbanks belonging to different banks may share the same GIO, so that a single GIO may be used in both read and write operations of different subbanks.
Referring to
According to the example implementation of
According to an example implementation, normal data and metadata corresponding to the normal data may be simultaneously written in the second bank B2. When a read operation is performed on the normal data ND and metadata MD written in the second bank B2, the normal data ND and the metadata MD may be simultaneously read through the two wordlines WL_M and WL_N by simultaneously activating the two wordlines WL_M and WL_N for each subbank (each of the 2-1-th subbank SB2-1 and 2-2 subbank SB2-2).
According to an example implementation, write operations may be simultaneously performed on normal data and simultaneously on metadata corresponding to the normal data. When write operations on normal data ND and on metadata MD are performed in the second bank B2, the normal data ND and the metadata MD may be simultaneously written through the two wordlines WL_M and WL_N by simultaneously activating the two wordlines WL_M and WL_N for each subbank (each of the 2-1-th subbank SB2-1 and the 2-2-th subbank SB2-2). For example, the first row decoder RD1 and the second row decoder RD2 may simultaneously select the normal data wordline WL_N and the metadata wordline WL_M, respectively. Additionally, a specific CSL may be selected through the first column decoder CD1 and the second column decoder CD2.
Then, a wordline and a CSL may be selected through row decoders RD1 and RD2 and the column decoders CD1 and CD2, and data on the selected wordline and the selected CSL, not shown, may be read or written through a GIO line connected to each subbank. For example, the same GIO may be used to read data from the subbank included in the first bank B1 as illustrated in
According to the above-described implementation, a single bank may include subbanks divided with a row decoder interposed therebetween, and thus different banks may share the same GIO. Therefore, when the normal data wordline and the metadata wordline are simultaneously activated, normal data and metadata may be simultaneously output without a timing loss. In addition, subbanks of different banks may share the same GIO to simultaneously output normal data and metadata without additional GIO.
Referring to
Allocating a wordline connected to one subbank for metadata of another subbank may refer to allocating the wordline for metadata corresponding to normal data to be written or read in another subbank. Therefore, according to an example implementation, wordlines for normal data and wordlines for metadata corresponding to the normal data may be provided to intersect each other in terms of a subbank.
Then, a ratio of the first wordline allocated for metadata among the first wordlines to the remaining first wordlines may be 1:(r−1), and a ratio of the second wordlines allocated for metadata among the second wordlines and the remaining second wordlines may be 1:(r−1).
For example, every r-th first wordline may be allocated to every 1st second wordline WL2-0 to every r-th second wordline WL2-(r−1) among the plurality of second wordlines WL2-0 to WL2-(32k−1). Every r-th second wordline may be allocated to every first wordline WL1-0 to every (r−1)-th wordline WL1-(r−1) among the plurality of first wordlines WL1-0 to WL1-(32k−1). For example, among the plurality of first wordlines WL1-0 to WL1-(32k−1) of the first subbank SB1, every r-th first wordline may be allocated to read or write metadata corresponding to normal data of every 1st second wordline to every (r−1)-th second wordline of the second subbank SB2 and among the plurality of second wordlines WL2-0 to WL2-(32k−1) of the second subbank SB2, every r-th first wordline may be allocated to read or write metadata corresponding to normal data of every 1st first wordline to every (r−1)-th first wordline.
For example, when n is 8 as illustrated in
According to
Referring to
According to
According to the above-described implementations, a portion of existing wordlines may be allocated for metadata to significantly satisfy a required normal/meta ratio without addition of new lines. For example, an allocation relationship between normal data wordlines and metadata wordlines may be established to intersect between subbanks, and thus normal data and metadata may be simultaneously output.
In this case, a single bank (for example, the first bank B1), divided into the first subbank SB1 and the second subbank SB2, represented by the example implementations of
The number of wordlines according to the above-described example implementations of
Referring to
In an example implementation, a column decoder CD connected to each subbank SB may include a plurality of CSL blocks CB and a single error correction code (ECC) block. Each of the CSL blocks CB and the ECC block may be configured to select a CSL based on a column address decoded from the column decoder CD. The CSL block CB and the ECC block may be arranged in a row direction d2 corresponding to the CSL. For example, among the plurality of MATs, MATs connected to a column corresponding to the ECC block may store parity bits generated from the ECC block.
In an example implementation, the ECC block may be disposed to correspond to a middle column among a plurality of columns formed by the plurality of MATs included in the subbank SB. For example, for a single subbank SB, a plurality of CSL blocks CB may be arranged symmetrically with respect to the ECC block. Accordingly, CSLs connected to the plurality of CSL blocks CB may also be arranged symmetrically with respect to the CSLs connected to the ECC block.
The plurality of CSL subsets L_CS0 to U_CS(i−1) may be connected to a plurality of MATs corresponding to a single CSL block CB. As illustrated in the drawing, a pair of CSL subsets may be selected from among the plurality of CSL subsets L_CS0 to U_CS(i−1) during a single access. For example, a pair of CSL subsets L_CS(i−2) and L_CS(i−1) (where, i is a positive integer) may be selected from a pair of CSL subsets L_CS0 and L_CS1 at a first side L with respect to the ECC block, and a pair of CSL subsets U_CS(i−2) and U_CS(i−1) may be selected from a pair of CSL subset U_CS0 and U_CS1 at a second side U with respect to the ECC block. In addition, a pair of CSL subsets M_CS0 and M_CS1 may be selected in the ECC block.
Referring to
Returning to
For example, a single bank may include one subbank SB and another subbank. In this case, when an access to normal data is performed through remaining wordlines, other than every r-th wordline, in one subbank SB, an access to metadata may be performed on every r-th wordline in another subbank. In this case, a pair of CSL subsets in another subbank or a portion of the pair of CSL subsets may be allocated to each of the remaining wordlines of the single subbank SB. Accordingly, when the access to normal data is performed on one of the remaining wordlines of the single subbank SB is performed, an access to metadata may be performed on the pair of CSL subsets or a portion of the pair of CSL subsets allocated to one of the remaining wordlines.
All CSL subsets may be selected in a normal-side subbank SB in which an access to normal data is performed. Accordingly, the access to normal data may be performed on the normal data wordline and all of the CSL subsets.
In an example implementation, a pair of CSL subsets L_CS0, L_CS1 to L_CS(i−2), and L_CS(i−1) included in the first side L, among the CSL subsets connected to the single subbank SB, and a pair of CSL subsets U_CS0, U_CS1 to U_CS(i−2), and U_CS(i−1) included in the second side U may be sequentially allocated from a pair of CSL subsets having a lowest index to the normal data wordline connected to the remaining subbanks SB.
In an example implementation, among the CSL subsets connected to the single subbank SB, the CSL subsets L_CS0 to L_CS(i−1) included in the first side L and the CSL subsets U_CS0 to U_CS(i−1) included in the second side U may be sequentially assigned from a CSL subset having a lowest index to the normal data wordlines connected to the remaining subbanks SB.
In
Here, m and n represent a range of a CSL subset to be selected from among the plurality of CSL subsets allocated to a single bank (or subbank) and are also positive integers. For example, m represents a lowest index among indices of the CSL subsets to be selected, and n represents a highest index among the indices of the CSL subsets to be selected.
The column decoder may select m-th to n-th CSL subsets from the CSL subsets on each of the first and second sides for a single bank (or subbank) based on CSLx[m:n], and may select an x-th CSL from a plurality of CSLs corresponding to the selected CSL subsets. For example, when m=0 and n=1 in
Here, x represents an index of a CSL to be selected from among a plurality of CSLs included in each pair of CSL subsets in
Returning to
In terms of the normal-side subbank NSB, an access to normal data may be performed on each of the first to seventh wordlines WL0 to WL6. In this case, the column select signal for the normal-side subbank NSB may be CSLx[0:15] to select all CSL subsets, and a value of x may range from 0 to 63, as illustrated in
Next, in terms of the meta-side subbank MSB, the eighth wordline WL7 may be allocated for the normal-side subbank NSB. In this case, the column select signal may be defined based on a wordline accessed in the normal-side subbank NSB. For example, according to the above-described implementation, a pair of CSL subsets of the meta-side subbank MSB may be sequentially allocated to a normal data wordline connected to the normal-side subbank NSB. For example, when the first wordline WL0 of the normal-side subbank NSB is accessed, m and n of the column select signal may be determined to be respectively 0 and 1 to select a pair of CSL subsets having the lowest index. Next, when the second wordline WL1 of the normal-side subbank NSB is accessed, m and n of the column select signal may be determined to be respectively 2 and 3 to select a pair of CSL subsets having the next index. When the last sixth wordline WL6 is accessed, m and n of the column select signal may be determined to be respectively 12 and 13 based on the above-described allocation relationship. According to the above-described implementation, the fifteenth and sixteenth CSL subsets on the meta side may not be allocated.
According to the above-described column select signal of
Referring to
In terms of the normal-side subbank NSB, an access to normal data may be performed on each of the first to fifteenth wordlines WL0 to WL14. As described above, a column select signal for the normal-side subbank NSB may be CSLx[0:15] to select all CSL subsets. Similarly, the sixteenth wordline WL15 of the normal-side subbank NSB may be allocated for the meta-side subbank MSB.
Next, in terms of the meta-side subbank MSB, the sixteenth wordline WL15 may be allocated for the normal-side subbank NSB. For example, according to the above-described implementation, the CSL subsets of the meta-side subbank MSB may be sequentially assigned from the CSL subset having the lowest index to the normal data wordline for normal data connected to the normal-side subbank NSB. Unlike
For example, when the first wordline WL0 of the normal-side subbank NSB is accessed, m of the column select signal may be determined to be 0 to select the CSL subset having the lowest index. Next, when the second wordline WL1 of the normal-side subbank NSB is accessed, m of the column select signal may be determined to be 1 to select the CSL subset having the next index. According to the above-described allocation relationship, when the last fifteenth wordline WL14 is accessed, m of the column select signal may be determined to be 15. According to the above-described implementation, the sixteenth CSL subset on the meta side may not be allocated.
According to the above-described column select signal of
Hereinafter, in
Referring to
According to an example implementation, every r-th wordline of the first subbank SB1 and the second subbank SB2 may be allocated for metadata. For example, when r=8, a 1st first wordline WL1-0 may be selected through the first row decoder RD1 connected to the first subbank SB1 to read or write normal data. In this case, an 8th second wordline WL2-7 may be selected through the second row decoder RD2 connected to the second subbank SB2 to read or write metadata corresponding to the normal data.
In addition, a pair of first-side CSL subsets L_CS2-0 and L_CS2-1 and a pair of second-side CSL subsets U_CS2-0 and U_CS2-1, among the second CSL subsets L_CS2-0 to U_CS2-15, may be allocated to the 1st first wordline WL1-0.
Then, the first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the first subbank SB1 that is a normal-side subbank, and the second column decoder CD2 may select a pair of first-side CSL subsets L_CS2-0 and L_CS2-1 and a pair of second-side CSL subsets U_CS2-0 and U_CS2, allocated for metadata, for the second subbank SB2 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the first column decoder CD1, and may be CSLx[0:1] (where x is one of 0 to 63) generated from the second column decoder CD2.
Accordingly, from the first subbank SB1 that is a normal-side subbank, normal data may be output from the 1st first wordline WL1-0 and the plurality of CSL subsets L_CS1-0 to U_CS1-15. In addition, from the second subbank SB2 that is a meta-side subbank, metadata corresponding to the normal data may be simultaneously output from the 8th second wordline WL2-7, the pair of first-side CSL subsets L_CS2-0 and L_CS2-1, and the pair of second-side CSL subsets U_CS2-0 and U_CS2-1.
Referring to
A pair of first-side CSL subsets L_CS2-2 and L_CS2-3 and a pair of second-side CSL subsets U_CS2-2 and U_CS2-3, among second CSL subsets L_CS2-0 to U_CS2-15, may be allocated to a 2nd first wordline WL1-1.
Then, the first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the first subbank SB1 that is a normal-side subbank, and the second column decoder CD2 may select a pair of first-side CSL subsets L_CS2-2 and L_CS2-3 and a pair of second-side CSL subsets U_CS2-2 and U_CS2, allocated for metadata, for a second subbank SB2 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the first column decoder CD1, and may be CSLx[2:3] (where x is one of 0 to 63) generated from the second column decoder CD2.
Accordingly, from the first subbank SB1 that is a normal-side subbank, normal data may be output from a 2nd first wordline WL1-1 and a plurality of first CSL subsets L_CS1-0 to U_CS1-15. In addition, from the second subbank SB2 that is a meta-side subbank, metadata corresponding to the normal data may be simultaneously output from an 8th second wordline WL2-7, a pair of first-side CSL subsets L_CS2-2 and L_CS2-3, and a pair of second-side subsets U_CS2-2 and U_CS2-3.
Every pair of CSL subsets of the second subbank SB2 may be sequentially allocated from a 3rd first wordline to a last wordline of the first subbank SB1.
Referring to
The first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the first subbank SB1 that is a normal-side subbank, and the second column decoder CD2 may select a pair of first-side CSL subsets L_CS2-12 and L_CS2-13 and a pair of second-side CSL subsets U_CS2-12 and U_CS2-13, allocated for metadata, for a second subbank SB2 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the first column decoder CD1, and may be CSLx[12:13] (where x is one of 0 to 63) generated from the second column decoder CD2.
Accordingly, from the first subbank SB1 that is a normal-side subbank, normal data may be output from a 7th first wordline WL1-6 and a plurality of first CSL subsets L_CS1-0 to U_CS1-15. In addition, from the second subbank SB2 that is a meta-side subbank, metadata corresponding to the normal data may be simultaneously output from an 8th second wordline WL2-7, a pair of first-side CSL subsets L_CS2-12 and L_CS2-13, and a pair of second-side subsets U_CS2-12 and U_CS2-13.
In this case, the pair of CSL subsets L_CS2-14, L_CS2-15, U_CS2-14, and U_CS2-15 corresponding to CSLx[14:15] in the second subbank SB2 may not be allocated to a wordline of the first subbank SB1.
Referring to
The first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the second subbank SB2 that is a normal-side subbank, and the second column decoder CD2 may select a pair of first-side CSL subsets L_CS1-0 and L_C1-1 and a pair of second-side CSL subsets U_CS1-0 and U_CS1-1, allocated for metadata, for a first subbank SB1 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the second column decoder CD2, and may be CSLx[0:1] (where x is one of 0 to 63) generated from the first column decoder CD2.
Accordingly, from the second subbank SB2 that is a normal-side subbank, normal data may be output from a 1st second wordline WL2-0 and a plurality of first CSL subsets L_CS1-0 to U_CS1-15. In addition, from the first subbank SB1 that is a meta-side subbank, metadata corresponding to the normal data may be simultaneously output from an 8th second wordline WL2-7, a pair of first-side CSL subsets L_CS1-0 and L_CS1-1, and a pair of second-side subsets U_CS1-0 and U_CS1-1.
Referring to
The first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the second subbank SB2 that is a normal-side subbank, and the second column decoder CD2 may select a pair of first-side CSL subsets L_CS1-2 and L_C1-3 and a pair of second-side CSL subsets U_CS1-2 and U_CS1-3, allocated for metadata, for a first subbank SB1 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the second column decoder CD2, and may be CSLx[2:3] (where x is one of 0 to 63) generated from the first column decoder CD2.
Every pair of CSL subsets of the first subbank SB1 may be sequentially allocated from a 3rd first wordline to the last wordline of the second subbank SB2.
Referring to
The first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the second subbank SB2 that is a normal-side subbank, and the second column decoder CD2 may select a pair of first-side CSL subsets L_CS1-12 and L_C1-13 and a pair of second-side CSL subsets U_CS1-12 and U_CS1-13, allocated for metadata, for a first subbank SB1 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the second column decoder CD2, and may be CSLx[12:13] (where x is one of 0 to 63) generated from the first column decoder CD2.
A pair of CSL subsets L_CS1-14, L_CS1-15, U_CS1-14, and U_CS1-15) corresponding to CSLx[14:15] in the first subbank SB1 may not be allocated to a wordline of the second subbank SB2.
Referring to
Among the second CSL subsets L_CS2-0 to U_CS2-15, a first-side CSL subset L_CS2-0 and a second-side CSL subset U_CS2-0 may be allocated to the first wordline WL1-0.
Then, the first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the first subbank SB1 that is a normal-side subbank, and the second column decoder CD2 may select a first-side CSL subset L_CS2-0 and a pair of second-side CSL subset U_CS2-0, allocated for metadata, for a second subbank SB2 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the first column decoder CD1, and may be CSLx[0] (where x is one of 0 to 63) generated from the second column decoder CD2.
Accordingly, from the first subbank SB1 that is a normal-side subbank, normal data may be output from a 1st first wordline WL1-0 and a plurality of first CSL subsets L_CS1-0 to U_CS1-15. In addition, from the second subbank SB2 that is a meta-side subbank, metadata corresponding to the normal data may be simultaneously output from a 16th second wordline WL2-15 and a single second-side subset U_CS2-0.
Referring to
Among the second CSL subsets L_CS2-0 to U_CS2-15, a first-side CSL subset L_CS2-1 and a second-side CSL subset U_CS2-1 may be allocated to the first wordline WL1-1.
Then, the first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the first subbank SB1 that is a normal-side subbank, and the second column decoder CD2 may select a first-side CSL subset L_CS2-1 and a second-side CSL subset U_CS2-1, allocated for metadata, for a second subbank SB2 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the first column decoder CD1, and may be CSLx[1] (where x is one of 0 to 63) generated from the second column decoder CD2.
Accordingly, from the first subbank SB1 that is a normal-side subbank, normal data may be output from a 2nd first wordline WL1-1 and a plurality of first CSL subsets L_CS1-0 to U_CS1-15. In addition, from the second subbank SB2 that is a meta-side subbank, metadata corresponding to the normal data may be simultaneously output from a 16th second wordline WL2-15, a first-side CSL subset L_CS2-1, and a second-side CSL subset U_CS2-1.
Every CSL subset of the second subbank SB2 may be sequentially allocated from a 3rd first wordline to a last wordline of the first subbank SB1.
Referring to
The first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the first subbank SB1 that is a normal-side subbank, and the second column decoder CD2 may select a first-side CSL subset L_CS2-14 and a second-side CSL subset U_CS2-14, allocated for metadata, for the second subbank SB2 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the first column decoder CD1, and may be CSLx[14] (where x is one of 0 to 63) generated from the second column decoder CD2.
Accordingly, from the first subbank SB1 that is a normal-side subbank, normal data may be output from a 15th first wordline WL1-14 and a plurality of first CSL subsets L_CS1-0 to U_CS1-15. In addition, from the second subbank SB2 that is a meta-side subbank, metadata corresponding to the normal data may be simultaneously output from a 16th second wordline WL2-15, a first-side CSL subset L_CS2-14, and a second-side CSL subset U_CS2-14.
In this case, the CSL subsets L_CS2-15 and U_CS2-15 corresponding to CSLx[15] in the second subbank SB2 may not be allocated to a wordline of the first subbank SB1.
Referring to
The first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the second subbank SB2 that is a normal-side subbank, and the second column decoder CD2 may select a first-side CSL subset L_CS1-0 and a second-side CSL subset U_CS1-0, allocated for metadata, for the first subbank SB1 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the second column decoder CD2, and may be CSLx[0] (where x is one of 0 to 63) generated from the first column decoder CD1.
Accordingly, from the second subbank SB2 that is a normal-side subbank, normal data may be output from a 1st second wordline WL2-0 and a plurality of first CSL subsets L_CS1-0 to U_CS1-15. In addition, from the first subbank SB2 that is a meta-side subbank, metadata corresponding to the normal data may be simultaneously output from an 8th second wordline WL2-7, a first-side CSL subset L_CS1-0, and a second-side CSL subset U_CS1-0.
Referring to
The first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the second subbank SB2 that is a normal-side subbank, and the second column decoder CD2 may select a first-side CSL subset L_CS1-1 and a second-side CSL subset U_CS1-1, allocated for metadata, for the first subbank SB1 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the second column decoder CD2, and may be CSLx[1] (where x is one of 0 to 63) generated from the first column decoder CD1.
Every CSL subset of the first subbank SB1 may be sequentially allocated from a 3rd first wordline to a last wordline of the second subbank SB2.
Referring to
The first column decoder CD1 may select all of the CSL subsets L_CS1-0 to U_CS1-15 for the second subbank SB2 that is a normal-side subbank, and the second column decoder CD2 may select a first-side CSL subset L_CS1-14 and a second-side CSL subset U_CS1-14, allocated for metadata, for the first subbank SB1 that is a meta-side subbank. In this case, a column select signal for selecting a CSL subset may be CSLx[0:15] (where x is one of 0 to 63) generated from the second column decoder CD2, and may be CSLx[14] (where x is one of 0 to 63) generated from the first column decoder CD1.
A pair of CSL subsets L_CS1-14, L_CS1-15, U_CS1-14, and U_CS1-15 corresponding to CSLx[15] in the first subbank SB1 may not be allocated to a wordline of the second subbank SB2.
According to the above-described implementations, at least a portion of the plurality of first CSL subsets L_CS1-0 to U_CS1-15 may be allocated to one of the remaining second wordlines, other than every r-th second wordline, among a plurality of second wordlines, and at least a portion of a plurality of second CSL subsets L_CS2-0 to U_CS2-15 may be allocated to one of the remaining first wordlines, other than every r-th first wordline, among a plurality of first wordlines.
According to an example implementation, when r is 8, at least a portion of the plurality of first CSL subsets L_CS1-0 to U_CS1-15 may be a pair of first CSL subsets L_CS1-0 to U_CS1-15 and at least a portion of the plurality of first CSL subsets L_CS1-0 to U_CS1-15 may be a pair of second CSL subsets L_CS2-0 to U_CS2-15.
Alternatively, according to an example implementation, when r is 16, at least a portion of the plurality of first CSL subsets L_CS1-0 to U_CS1-15 may be a single first CSL subset L_CS1-0 to U_CS1-15 and at least a portion of the plurality of first CSL subsets L_CS1-0 to U_CS1-15 may be a single second CSL subset L_CS2-0 to U_CS2-15.
The first row decoder RD1 connected to the first subbank SB1 may be configured to select one of the plurality of first wordlines, and the first column decoder CD1 may be configured to select a first CSL subset L_CS1-0 to U_CS1-15 from among the plurality of CSLs. In addition, the second row decoder RD2 connected to the second subbank SB2 may be configured to select one of the plurality of second wordlines, and the second column decoder CD2 may be configured to select the second row decoder RD2 and a second CSL subset L_CS2-0 to U_CS2-15 from among the plurality of CSLs. In an example implementation, the second row decoder RD2 may select a single second wordline allocated to a single first wordline of every r-th second wordline among the plurality of second wordlines, based on the first row decoder RD1 selecting one of the remaining first wordlines, other than every r-th first wordline, from among the plurality of first wordlines.
Alternatively, in an example implementation, the first row decoder RD1 may select a single first wordline allocated to a single second wordline of every r-th first wordline from among the plurality of first wordlines, based on the second row decoder RD2 selecting one of the remaining second wordlines, other than every r-th second wordline, from among the plurality of second wordlines
According to the above-described implementations, when one of the subbanks included in a single bank operates as a normal-side subbank, the remaining subbanks may operate as meta-side subbanks. For example, a CSL subset of the meta-side subbank is allocated for each wordline of the normal-side subbank, a required normal/meta ratio may be significantly satisfied without chip size overhead.
Referring to
A CSL, connected to a column decoder CD, may be connected to the plurality of subset banks SSB1 to SSBN. A CSL may operate individually for each of the subset banks SSB1 to SSBN. For example, among CSLs, CSLs connected to a portion of the subset banks SSB1 to SSBN may be enabled, and CSLs connected to another portion of subset banks SSB1 to SSBN may be disabled.
Referring to
In this case, when the subbank SB is configured to include a plurality of subset banks SSB1 to SSBN in a row direction d2, an allocated CSL CSL_A may include only one of the plurality of subset banks SSB1 to SSBN. Based on the fact that at least a portion of CSLs (or a pair of CSLs) of a plurality of CSL subsets are activated for one of the plurality of subset banks SSB1 to SSBN, only a region corresponding to one of the subset banks SSB1 to SSBN may be enabled in every r-th wordline. Accordingly, according to an example implementation, only wordlines of a subset bank connected to the allocated CSL CSL_A may be enabled, and wordlines of the remaining subset banks may be disabled.
For example, in the case of
According to the above-described implementations, in a memory device, only a wordline EN_WL of a subset bank to which allocated CSL CSL_A is connected, among all subbanks, may operate when a subbank SB is used as a meta-side subbank SB. This is because in this case, CSLs of the remaining subset banks included in the meta-side subbank SB are not used for an access to metadata. As a result, according to example implementations, power consumption may be reduced during normal data and metadata access operations may be reduced.
As set forth above, according to example implementations, a volatile memory device for allocating specific data may be provided.
While this disclosure contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed. Certain features that are described in this disclosure in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations, one or more features from a combination can in some cases be excised from the combination, and the combination may be directed to a subcombination or variation of a subcombination.
While example implementations have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2023-0066576 | May 2023 | KR | national |
10-2023-0122763 | Sep 2023 | KR | national |