Patent Application
20180149680
This disclosure relates generally to current sensors, and in particular, but not exclusively to electronic circuits for the voltage buffer of an ionic current sensor.
Advances in micro-miniaturization within the semiconductor industry in recent years have enabled biotechnologists to begin packing traditionally bulky sensing tools into smaller and smaller form factors, onto so-called biochips. Despite these advances in micro-miniaturization there remains a need to (1) further miniaturize the chips, (2) to increase their throughput, and/or (2) to improve their performance For example, for many current sensors, such as the current sensors utilized in biochips, the sensed current is typically a very small signal. Thus, a low-noise front-end design may be important in maintaining the accuracy and/or reliability of the sensor.
The following presents a simplified summary relating to one or more aspects and/or embodiments associated with the mechanisms disclosed herein for a voltage buffer of a current sensor. As such, the following summary should not be considered an extensive overview relating to all contemplated aspects and/or embodiments, nor should the following summary be regarded to identify key or critical elements relating to all contemplated aspects and/or embodiments or to delineate the scope associated with any particular aspect and/or embodiment. Accordingly, the following summary presents certain concepts relating to one or more aspects and/or embodiments relating to the mechanisms disclosed herein to buffer a voltage of a current sensor in a simplified form to precede the detailed description presented below.
According to one aspect, a sensing cell includes a current sensor, an integrating capacitor, and a voltage buffer. The integrating capacitor is configured to store a voltage representative of a current signal generated by the current sensor. The voltage buffer is coupled to provide a buffered voltage to a readout line and includes a first transistor and a second transistor. The first transistor is coupled to receive the voltage stored on the integrating capacitor and the second transistor is coupled to the readout line. The second transistor is configured to compensate for a body effect of the first transistor.
According to another aspect, a sensing cell includes means for generating a current signal, means for storing a voltage representative of the current signal, and a voltage buffer. The voltage buffer is coupled to the means for storing the voltage and is configured to generate a buffered voltage. The voltage buffer includes a first transistor and a second transistor. The first transistor is coupled to receive the voltage representative of the current signal and the second transistor is coupled to generate the buffered voltage and is configured to compensate for a body effect of the first transistor.
According to yet another aspect, a complementary metal-oxide-semiconductor (CMOS) ionic current sensor array includes a plurality of sensing cells, where each sensing cell includes an ionic current sensor, an integrating capacitor, a sense field effect transistor (FET), and a voltage buffer. The ionic current sensor is configured to generate a current signal and the integrating capacitor is configured to store a voltage representative of the current signal. The sense FET is coupled between the integrating capacitor and the current sensor to provide the current signal to the integrating capacitor and the voltage buffer is coupled between the integrating capacitor and a column readout line to provide a buffered voltage to the column readout line. The voltage buffer includes a first FET, a second FET, a first current source, and a second current source. The first FET is coupled to receive the voltage stored on the integrating capacitor and the second FET is coupled to the column readout line and also is configured to compensate for a body effect of the first FET. The first current source is coupled to the first and second FETs and the second current source is coupled to the second FET.
The accompanying drawings are presented to aid in the description of present disclosure and are provided solely for illustration of the embodiments and not limitation thereof.
Aspects of the present disclosure are disclosed in the following description and related drawings directed to specific examples. Alternate implementations may be devised without departing from the scope of the present disclosure. Additionally, well-known aspects will not be described in detail or will be omitted so as not to obscure the relevant details of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the present disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Further, some embodiments may be described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits (e.g., application specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. Additionally, these sequence of actions described herein can be considered to be embodied entirely within any form of computer readable storage medium having stored therein a corresponding set of computer instructions that upon execution would cause an associated processor to perform the functionality described herein. Thus, the various aspects of the present disclosure may be embodied in a number of different forms, all of which have been contemplated to be within the scope of the claimed subject matter. In addition, for each of the embodiments described herein, the corresponding form of any such embodiments may be described herein as, for example, “means for” or “logic configured to” perform the described action.
In operation, a voltage potential 106 is applied across the opening 108, which may be immersed in a conducting fluid. When the voltage potential 106 is applied, a small ionic current 110 attributable to the conduction of ions across the opening 108 can be sensed. The amount of ionic current 110 that is sensed is relative to the size (i.e., internal diameter of opening 108). When a molecule, such as a DNA or RNA molecule, passes through the opening 108, it can partially or completely block the opening 108, causing a change in a magnitude of the ionic current 110. It has been shown that such an ionic current blockade can be correlated with the base pair sequence of DNA or RNA molecules.
In practice, nanopore-based DNA sequencers may include a large array of complementary metal-oxide-semiconductor (CMOS) ionic current sensors, such as ionic current sensor 102. Each ionic current sensor of the array may be included in a respective sensing cell that includes electronic circuitry for controlling the operation and monitoring the output of each ionic current sensor 102. For example, each sensing cell may be configured to generate the voltage potential 106 and to sense the ionic current 110 generated by a respective ionic current sensor. In some applications the ionic current 110 is in the range of 10 pA-100 pA. In other words, the sensed current (i.e., ionic current 110) is a very small signal. Thus, a low-noise front-end design may be important in maintaining the accuracy and/or reliability of the sensor. Among front-end circuits, a good voltage buffer for generating the voltage representative of the ionic current 110 is desired which provides a gain that is close to unity and also provides a substantially linear output.
In one example, array 205 is a two-dimensional array of sensing cells (e.g., sensing cells SC1, . . . , SCn). Each sensing cell may be a complementary metal-oxide-semiconductor (“CMOS”) sensing cell, where each sensing cell includes at least one ionic current sensor, such as ionic current sensor 102 of
Control circuitry 220 is coupled to array 205 to control operational characteristics of array 205 via one or more control signals 235. For example, control circuitry 220 may generate a row select, column select, and/or a reset signal for controlling acquisition of the ionic current values by the sensing cells.
As illustrated in
After each sensing cell has sensed its current, the current data or values are readout by readout circuitry 210 which are then transferred to function logic 215. Readout circuitry 210 may include amplification circuitry, analog-to-digital conversion circuitry, or otherwise. Function logic 215 may simply storage the current values or even analyze ionic current values to determine the DNA/RNA sequencing. In one example, readout circuitry 210 may readout a row of ionic current values at a time along column readout lines 225 or may readout the current values using a variety of other techniques (not illustrated), such as a serial readout or a full parallel readout of all sensing cells simultaneously. In one example, the current values are readout via column readout lines 225 in the form of a buffered voltage generated within each sensing cell. However, as mentioned above, the current signal sensed within each sensing cell is a very small signal. Thus, the front-end circuit including a voltage buffer within each sensing cell is designed to provide a gain that is close to unity and also to provide a substantially linear output.
By way of example,
Sensing cell 300 of
During a readout operation of the current sensor 304, switch S1 may receive a pre-charge signal (not shown) to control switch S1 to pre-charge the integrating capacitor C1 to the supply voltage VDD. In some implementations, switch S1 may be referred to as a reset switch and may include one or more transistors. Amplifier 302 may be coupled to provide the reference voltage V_REF to bias the current sensor 304. In one example, amplifier 302 may be configured to provide the reference voltage V_REF based on a bias voltage received via a bias generator (e.g., bias voltage 240 received from bias generator 230 of
Thus, in one example, the voltage V_1 across the integrating capacitor C1 may be representative of the sensed current 317. In one example, the charge stored in the capacitor is represented by Q=CV, where Q is the charge, C is capacitance of capacitor C1 and V is the voltage V_1 across the capacitor. The charge is integration of the current over time. Thus, as current is allowed to flow through the capacitor C1, the charge and voltage across the capacitor C1 linearly increases over time. Source follower transistor 308 and current source 309 are configured as a voltage buffer between integrating capacitor C1 and the column readout line. Switch S2 is coupled between the source follower transistor 308 and the column readout line to provide the buffered voltage V_2 in response to a transfer signal (not shown). As shown in
The transfer signal, the pre-charge (e.g., reset) signal, supply voltage VDD, and the common reference 310 (e.g., ground) may be routed in the sensing cell 300 by way of metal interconnect layers (i.e., routings) included in the array (e.g., array 205).
Although
As mentioned above, the source follower transistor 308 and current source 309 are configured as a voltage buffer to provide the buffered voltage V_2 to the column readout line. For example, the gate G of the source follower transistor 308 is coupled to receive the voltage V_1 that is stored on the integrating capacitor C1 and in response thereto, generate the buffered voltage V_2 at the source S of the source follower transistor 308. However, the source follower transistor 308 of
As shown in
In one example, the above-referenced couplings of the first transistor t1, second transistor t2, first current source I1, and second current source I2 are direct couplings. That is, a direct coupling may refer to a connection without any intervening active components there between. For example, the source S of transistor t1 may be directly coupled to the first current source I1 without any intervening active components (e.g., transistor, diode, integrated circuit, etc.) between the source S and the first current source I1. In some implementations, a direct coupling without an intervening active component may still include an intervening passive component, in accordance with the teachings herein. That is, a passive component (e.g., a resistor) may be connected in between the gate G of the second transistor t2 and the output 506 such that a current or voltage is still allowed to propagate from the gate G to the output 506. In yet another example, the above-referenced couplings may refer to a direct connection without any intervening active or passive components there between. For example, the gate G of the first transistor t1 may be directly connected to the integrating capacitor C1 without any intervening active components (e.g., transistor, diode, etc.) and without any intervening passive components (e.g., resistor, capacitor, etc.). However, a direct connection between the illustrated components of voltage buffer 502 may still include a mechanism for passing signals there between such as a conductor, metal trace, via, lead, wire, etc.
In one aspect, the first transistor t1 and the first current source I1 are configured to operate as a source follower similar to the source follower configuration of
In one example, the overall gain of the voltage buffer 502 is proportional to the intrinsic resistance of the second current source I2. In particular, the gain of voltage buffer 502 may be expressed as
where gm is the transconductance of the second transistor t2, gmb is the gain due to the body effect of the second transistor t2, gds is the drain-to-source gain of the second transistor t2, and Rs is the intrinsic resistance of the second current source I2.
Although
In some implementations, the voltage buffer 502 is configured such that the voltage at the gate G of the first transistor t1 is substantially equal to the voltage at the gate G of the second transistor t2. However, as mentioned above, the second current source I2 may include an intrinsic resistance that results in a voltage drop across the second current source I2. Thus, in some examples the relative sizing of the first transistor t1 to the second transistor t2 may be configured to adjust for this. In one example, the size of the second transistor t2 may be larger than the size of the first transistor t1. In some aspects, the size of the transistor may refer to the channel width. Thus, a larger size refers to a larger channel width. In another example, the size of the transistor refers to a ratio of the transistors channel width to channel length (e.g., channel width/channel length). Thus, in this example, a larger size refers to a transistor that has a larger ratio of channel width to channel length.
In lieu of, or in addition to, having a size of the first transistor t1 different than the size of the second transistor t2, the voltage buffer 502 may be configured to utilize two separate supply voltages to compensate for the voltage drop across the second current source I2. By way of example,
As shown in
As shown above, the voltage drop across the second current source I2 may be compensated for to ensure a sufficient Vds across the second transistor t2 by utilizing separate supply voltages for the voltage buffer 602. In one example, the values of the first and second supply voltages are selected such that the size of the first transistor t1 can be the same as the size of the second transistor t2. In yet another example, the values of the first and second supply voltages are selected such that the size of the second transistor t2 is smaller than a size of the first transistor t1. That is, in the illustrated example of the voltage buffer 602 of
Thus, the example circuitry architectures of voltage buffers 502 and 602 provide for an improvement in linearity and gain when compared to the circuitry architecture of the voltage buffer 308 of
Those of skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Further, those of skill in the art will appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. By way of example, for each of the embodiments described herein, the corresponding form of any such embodiments may be described herein as, a “means for” performing the described action. Thus, a “means for generating a current signal” may correspond to, for example, ionic current sensor 102 of
The methods, sequences and/or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
Accordingly, an aspect of the present disclosure can include a computer readable media embodying a method for reading out one or more current values from a current sensor array. Accordingly, aspects of the present disclosure are not limited to illustrated examples and any means for performing the functionality described herein are encompassed by the scope of the present disclosure.
While the foregoing disclosure shows illustrative embodiments, it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with examples described herein need not be performed in any particular order. Furthermore, although elements of the disclosed examples may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
