Patent Application
20170115340
1. Field of the Invention
This invention is related to a voltage calibration circuit, and more particularly, to a voltage calibration circuit that is capable of updating the output voltage to be calibrated automatically.
2. Description of the Prior Art
Since complexity of integrated circuits has increased over time, the system may require a variety of voltage sources to drive different functional elements within one integrated circuit. However, after complicated manufacturing processes, semiconductor components may have different characteristics from each other, which makes the voltage generated by a voltage source be different from its target voltage. For example, a voltage source designed to supply 1.5V may output 1.2V instead when using default parameters due to variations in the manufacturing process. To avoid skewed operations of functional elements caused by the mismatch of voltages, the parameters of the voltage sources have to be fine-tuned after the manufacturing process so as to bring their output voltages closer to the target values.
To shorten the time for calibration, the integrated circuit of prior art usually includes a built-in self-test (BIST) circuit, which can be connected to an external tester. The tester can provide the target voltage required by the integrated circuit. The BIST circuit can compare the target voltage and the voltage outputted by the voltage source, and can keep adjusting the parameters of the voltage source until the voltage outputted by the voltage source is close enough to the target voltage. Afterward, the adjusted parameters can be used as the parameters for the voltage source to output the wanted voltage. During the testing process, the tester and the BIST circuit should be aware of the statuses from each other to perform the corresponding operations. For example, the tester needs to know whether the BIST circuit has already completed the calibration so that the tester can provide a next target voltage, and the BIST circuit needs to know whether the tester has already updated the target voltage so that the BIST circuit can move on to a next voltage source to be calibrated. Therefore, the integrated circuit usually reserves a bus for communication between these two circuits. In the prior art, the bus for such communication may require more than 8 pins. Since the package used by an integrated circuit may partly depend on the number of pins, the number of pins of the integrated circuit can significantly affect the area required by the integrated circuit. Therefore, how to reduce the pins required by the communication between the tester and the BIST circuit has become a critical issue to be resolved.
One embodiment of the present invention discloses a voltage calibration circuit. The voltage calibration circuit includes a voltage output circuit, a first amplifier, a notification circuit, and a built-in self-test circuit. The voltage output circuit comprises a plurality of voltage sources to be calibrated, and can select a first voltage source from the plurality of voltage sources to output an output voltage to be calibrated according to a selection signal. The first amplifier has a first input terminal configured to receive the output voltage, a second input terminal configured to receive a reference voltage corresponding to the first voltage source, and an output terminal. The notification circuit is coupled to the output terminal of the first amplifier. The notification circuit can output a notification signal according to an indication voltage, the reference voltage, and a voltage at the output terminal of the first amplifier. The built-in self-test circuit is coupled to the notification circuit, the first amplifier, and the voltage output circuit, and the built-in self-test circuit can update the selection signal according to the notification signal so as to enable the voltage output circuit to select a second voltage source from the plurality of voltage sources accordingly.
One embodiment of the present invention discloses a voltage calibration system. The voltage calibration system includes a voltage calibration circuit and a test circuit. The voltage calibration circuit includes a voltage output circuit, a first amplifier, a notification circuit, and a built-in self-test circuit. The voltage output circuit comprises a plurality of voltage sources to be calibrated, and can select a first voltage source from the plurality of voltage sources to output an output voltage to be calibrated according to a selection signal. The first amplifier has a first input terminal configured to receive the output voltage, a second input terminal configured to receive a reference voltage corresponding to the first voltage source, and an output terminal. The notification circuit is coupled to the output terminal of the first amplifier. The notification circuit can output a notification signal according to an indication voltage, the reference voltage, and a voltage at the output terminal of the first amplifier. The built-in self-test circuit is coupled to the notification circuit, the first amplifier, and the voltage output circuit. The built-in self-test circuit can output a completion signal according to the voltage at the output terminal of the first amplifier and update the selection signal according to the notification signal so as to enable the voltage output circuit to select a second voltage source from the plurality of voltage sources accordingly. The test circuit can provide the reference voltage corresponding to the first voltage source, and adjust the reference voltage according to the completion signal. The adjusted reference voltage is corresponding to the second voltage source.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The voltage output circuit 110 includes a plurality of voltage sources 112A, 112B, and 112C. The voltage sources 112A, 112B, and 112C can provide different voltages required by the chip 10. For example, the voltage source 112A can provide a target voltage of 1.5V, the voltage source 112B can provide a target voltage of 1.2V, and the voltage source 112C can provide a target voltage of 1.8V. Since the characteristics of the voltage sources 112A, 112B, and 112C may not be the same as expected due to the semiconductor manufacturing process, the voltages outputted by the voltage sources 112A, 112B, and 112C may be different from their target voltages when using default parameters. Therefore, calibration is required.
The voltage output circuit 110 can select a voltage source from the voltage sources 112A, 112B, and 112C to be calibrated according to a selection signal SCV. For example, in
The first amplifier 120 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first amplifier 120 can receive the output voltage VC to be calibrated, the second input terminal of the first amplifier 120 can receive a reference voltage Vref corresponding to the first voltage source 112A, in this case, the reference voltage Vref is 1.5V. In some embodiments of the present invention, the reference voltage Vref is provided by an external circuit.
The BIST circuit 140 is coupled to the first amplifier 120 and the voltage output circuit 110, and can calibrate the voltage output circuit 110 according to a voltage at the output terminal of the first amplifier 120. In other words, when the BIST circuit 140 needs to calibrate the voltage source 112A, the BIST circuit 140 can output the selection signal SCV corresponding to the voltage source to be calibrated first so that the voltage output circuit 110 can output the output voltage VC to be calibrated according to the voltage VCA outputted by the voltage source 112A.
The voltage source 112A can output the voltage VCA according to its default parameters first, and the BIST circuit 140 can derive the relation between voltage VC and the reference voltage Vref according to the voltage at the output terminal of the first amplifier 120. In some embodiments of the present invention, the first input terminal of the first amplifier 120 can be a positive terminal, and the second input terminal of the first amplifier 120 can be a negative terminal. In this case, when the voltage VC is greater than the reference voltage Vref, the voltage at the output terminal of the first amplifier 120 would be at a high voltage level, and when the voltage VC is smaller than the reference voltage Vref, the voltage at the output terminal of the first amplifier 120 would be at a low voltage level.
For example, when the voltage VC is 1.32 and the reference voltage Vref is 1.5V, the voltage at the output terminal of the first amplifier 120 is at the low voltage level. At this time, the BIST circuit 140 can control the voltage output circuit 110 to adjust the parameters of the voltage source 112A so as to cause the voltage source 112A to output a higher voltage VCA1. If the voltage VCA1 is 1.44V, for example, since the voltage VCA1 is still smaller than the reference voltage Vref, the BIST circuit 140 can keep adjusting the parameters of the voltage source 112A to cause the voltage source 112A to output an even higher voltage VCA2, which may be 1.56V, for example. Namely, the voltage source 112A can sequentially output a plurality of voltages VCA, VCA1, and VCA2 to be calibrated according to the control of the BIST circuit 140.
Since the voltage VCA2 is greater than Vref, the voltage at the output terminal of the first amplifier 120 would change to the high voltage level. The BIST circuit 140 can determine that the voltage source 112A has completed calibration when the voltage at the output terminal of the first amplifier changes from the low voltage level to the high voltage level, and BIST circuit 140 can save the parameters at that time as calibrated parameters of the voltage source 112A. When the voltage source 112A uses the calibrated parameters, the voltage outputted by the voltage source 112A would be closer to its target voltage than the voltage it generates before calibration.
In some embodiments of the present invention, the BIST circuit 140 can also determine that the voltage source 112A has completed calibration when the voltage at the output terminal of the first amplifier 120 changes from the high voltage level to the low voltage level, when the voltage at the output terminal of the first amplifier 120 changes, or when the voltage VC is close enough to the reference voltage Vref.
After the calibration of the voltage source 112A is completed, the BIST circuit 140 can select a next voltage source from the voltage output circuit 110 to be calibrated. However, before the calibration of the next voltage source, the BIST circuit 140 must confirm whether the reference voltage Vref has been changed to a target voltage of the next voltage source, so that the BIST circuit 140 can move on and repeat the aforesaid calibration process. In this case, the BIST circuit 140 can be informed if the reference voltage Vref has been updated properly according to the notification signal SCHG outputted by the notification circuit 130.
The notification circuit 130 is coupled to the output terminal of the first amplifier 120. The notification circuit 130 can receive the indication voltage VI, the reference voltage Vref, and the voltage at the output terminal of the first amplifier 120, and can output the notification signal SCHG according to the indication voltage VI, the reference voltage Vref, and the voltage at the output terminal of the first amplifier 120. The indication voltage VI and the output voltage VC have a first fixed voltage difference ΔV1, ex., 0.2V.
In
If the target voltage of the first voltage source and the target voltage of the second voltage source (the next voltage source to be calibrated) have a second fixed voltage difference ΔV2, then the second fixed voltage difference ΔV2 should be greater than the first fixed voltage difference ΔV1 between the output voltage VC and the indication voltage VI. In addition, if two of the voltages VCA, VCA1, and VCA2 have a third fixed voltage difference ΔV3, ex. 0.12V in the aforesaid example, then the third fixed voltage difference ΔV3 should be no greater than the first fixed voltage difference ΔV1.
Table 1 shows the reference voltage Vref, the output voltage VC, the indication voltage VI, voltages at the output terminals of the amplifier 120 and 132, and voltage of the notification signal SCHG in different periods after the voltage source 112A completes calibration.
According to Table 1, during period T1, the voltage source 112A has finished calibration but the reference voltage Vref has not been updated yet. The reference voltage Vref remains as the target voltage 1.5V of the voltage source 112A and the output voltage VC is at 1.56V. In this case, the voltage at the output terminal of the first amplifier 120 is at the high voltage level H. Also, since the indication voltage VI and the output voltage VC have the first fixed voltage difference ΔV1, that is, the indication voltage VI is at 1.36V, which is smaller than the reference voltage Vref, the voltage at the output terminal of the second amplifier 132 is at the low voltage level L. Therefore, the voltage at the output terminal of the exclusive OR gate 134 is at the high voltage level H, namely, the notification signal SCHG is at the high voltage level H.
During period T2, the voltage source 112A has finished calibration, and the reference voltage Vref has been updated to the target voltage of the next voltage source to be calibrated. For example, if the voltage source 112B is the second voltage source to be calibrated next, the reference voltage Vref would be updated to the target voltage 1.2V of the voltage source 112B. In this case, since the BIST circuit 140 has not updated the selection signal SCV yet, the output voltage VC would remain at the voltage VCA2 outputted from the voltage source 112A, that is, 1.56V. Therefore, the voltage at the output terminal of the first amplifier 120 remains at the high voltage level H.
In addition, the second fixed voltage difference ΔV2 is greater than the first fixed voltage difference ΔV1, that is, the second fixed voltage difference ΔV2 between the target voltage 1.5V of the voltage source 112A and the target voltage 1.2V of the voltage source 112B is 0.3V, which is greater than the first fixed voltage difference ΔV1, which is 0.2V. Therefore, the indication voltage VI would be greater than the updated reference voltage Vref, which makes the voltage at the output terminal of the second amplifier 132 to be at the high voltage level H, and further makes the voltage at the output terminal of the exclusive OR gate 134 to be at the low voltage level L. Namely, the notification signal SCHG would be at the low voltage level L.
Table 2 shows the reference voltage Vref, the output voltage VC, the indication voltage VI, voltages at the output terminals of the amplifier 120 and 132, and voltage of the notification signal SCHG in different periods after the voltage source 112A completes calibration according to another embodiment.
According to Table 1, during period T1, the voltage source 112A has finished calibration, however, the reference voltage Vref remains at the target voltage 1.5V of the voltage source 112A and the output voltage VC is at 1.56V. In this case, the voltage at the output terminal of the first amplifier 120 is at the high voltage level H. Also, since the indication voltage VI is smaller than the reference voltage Vref, the voltage at the output terminal of the second amplifier 132 is at the low voltage level L. Therefore, the voltage at the output terminal of the exclusive OR gate 134 is at the high voltage level H, namely, the notification signal SCHG is at the high voltage level H.
During period T3, the voltage source 112A has finished calibration, and the reference voltage Vref has been updated to the target voltage of the next voltage source to be calibrated. In this case, if the voltage source 112C is the second voltage source to be calibrated next, the reference voltage Vref would be updated to the target voltage 1.8V of the voltage source 112C. In this case, since the BIST circuit 140 has not updated the selection signal SCV yet, the output voltage VC would remain at the voltage VCA2 outputted from the voltage source 112A, that is, 1.56V. Since the second fixed voltage difference ΔV2 is greater than the first fixed voltage difference ΔV1, that is, the second fixed voltage difference ΔV2 between the target voltage 1.5V of the voltage source 112A and the target voltage 1.8V of the voltage source 112C is 0.3V, which is greater than the first fixed voltage difference ΔV1, which is 0.2V. Therefore, the output voltage VC would be smaller than the updated reference voltage Vref, causing the voltage at the output terminal of the first amplifier 120 to change to the low voltage level L.
In addition, since the indication voltage VI would be smaller than the updated reference voltage Vref, the voltage at the output terminal of the second amplifier 132 remains at the low voltage level L, which makes the voltage at the output terminal of the exclusive OR gate 134 to be at the low voltage level L. Namely, the notification signal SCHG would be at the low voltage level L.
In other words, in Table 1 and Table 2, whether the next voltage source to be calibrated is the voltage source 112B or the voltage source 112C, the notification signal SCHG would change from the high voltage level H to the low voltage level L when the reference voltage Vref is updated to the target voltage of the next voltage source to be calibrated, as long as the fixed voltage difference between the target voltages of the voltage sources 112A and 112B and the fixed voltage difference between the target voltages of the voltage sources 112A and 112C are greater than the first fixed voltage difference ΔV1 between the output voltage VC and the indication voltage VI. Therefore, according to the notification signal SCHG, the BIST circuit 140 can determine whether the reference voltage Vref provided by the external circuit has been updated or not. When the notification signal SCHG changes from the high voltage level H to the low voltage level L, the BIST circuit 140 can update the selection signal SCV to control the voltage output circuit 110 to select the voltage source 112B or 112C to be the second voltage source to be calibrated next.
In some embodiments of the present invention, the voltage output circuit 100 can further include a voltage gap element 150. The voltage gap element 150 is coupled to the voltage output circuit 110 and the first input terminal of the second amplifier 132. The voltage gap element 150 can output the indication voltage VI according to the output voltage VC. In
In some embodiments of the present invention, the voltage gap element 150 of the voltage calibration circuit 100 can also be implemented by a diode. The anode of the diode can receive the output voltage VC and the cathode of the diode can output the indication voltage VI.
Since the indication voltage output circuit 250 can generate the indication voltage VI by different indication voltage sources 252A, 252B, and 252C, the user may configure the indication voltage output circuit 250 to adjust the value of the first fixed voltage difference ΔV1 between the indication voltage VI and the output voltage VC according to system requirements, which ensures that the first fixed voltage difference ΔV1 is smaller than the second fixed voltage difference ΔV2 and greater than or equal to the third fixed voltage difference ΔV3. In a better embodiment of the present invention, the third fixed voltage difference ΔV3 can be substantially equal to the first fixed voltage difference ΔV1. In this case, the indication voltage sources 252A, 252B, and 252C can have the same structures as the voltage sources 112A, 112B, and 112C, however, the trim codes of the indication voltage sources 252A, 252B, and 252C are one phase behind the trim codes of the voltage sources 112A, 112B, and 112C. For example, during the aforesaid processes, when the voltage source 112A outputs the voltage VCA1 at 1.44V according to the trim code, the indication voltage source 252A can use the trim code the voltage source 112A used in a previous phase to output the indication voltage VI at 1.32V. Similarly, when the voltage source 112A outputs the voltage VCA2 at 1.56V according to the trim code of next phase, the indication voltage source 252A can use the trim code the voltage source 112A used in a previous phase to output the indication voltage VI at 1.44V. Therefore, the indication voltage sources 252A, 252B, and 252C can have the same structures as the voltage sources 112A, 112B, and 112C, and there is no need to redesign the circuits of the indication voltage sources 252A, 252B, and 252C.
Consequently, the voltage calibration circuit 200 can determine whether the reference voltage Vref provided by the external circuit has been updated or not according to the notification signal SCHG. When the notification signal SCHG changes from the high voltage level H to the low voltage level L, the selection signal SCV is updated so that the voltage output circuit 110 can select the voltage source to be calibrated next accordingly.
After finishing calibration of the voltage source 112A, the BIST circuit 140 can output a completion signal Sdone through a second pin P2 of the chip 10 to the test circuit 310. In some embodiments of the present invention, the BIST circuit 140 can output a completion signal Sdone when the voltage at the output terminal of the first amplifier 120 changes from the high voltage level to the low voltage level. The test circuit 310 can adjust the reference voltage Vref according to the completion signal Sdone so that the adjusted reference Vref voltage will be corresponding to the second voltage source to be calibrate, for example, the voltage source 112B. When the reference voltage Vref is updated to the target voltage 1.2V of the voltage source 112B to be calibrated, the notification circuit 130 would update the notification signal SCHG according to the aforesaid operating principles. Therefore, the voltage calibration circuit 100 can determine whether the reference voltage Vref provided by the test circuit 310 has been updated or not according to the notification signal SCHG. Also, when the notification signal SCHG changes from the high voltage level H to the low voltage level L, the voltage calibration circuit 100 can update the selection signal SCV so that the voltage output circuit 110 can change to select the voltage source 112B for the following calibration process.
In summary, the voltage calibration circuit and the voltage calibration system provided by the embodiments of the present invention can determine whether the reference voltage has been updated or not according to the notification circuit so that the voltage calibration circuit can perform the following calibration process without using external circuits to update the status. Therefore, the issue of big circuit area requirement and the difficulty of wire connection caused by the great number of pins in the prior art can be solved.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 104135202 | Oct 2015 | TW | national |
