Patent Grant
7221920
This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2003-201199 filed on Jul. 24, 2003; the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a voltage controlled oscillator using a film bulk acoustic resonator and, more particularly, to a voltage controlled oscillator having a variable oscillation frequency, a communication apparatus and a frequency synthesizer using the same.
2. Description of the Related Art
In recent years, the market for a wireless communication system including a mobile phone and the like, has expanded, and at the same time, mobile communications services have been increasingly sophisticated. Moreover, it is expected that a local area network (LAN) system will rapidly become widespread in coming years. In these wireless communication systems, a radio frequency (RF) band of 2 GHz, 5 GHz, or more, is generally used.
In the RF band wireless communication systems, frequency synthesizers are used which are capable of oscillating in frequency bands required in the respective systems. The use of a quartz oscillator makes it possible to generate a highly precise reference frequency. However, a voltage controlled oscillator (VCO) is generally used in an RF band where the quartz oscillator cannot directly oscillate. Although a VCO alone cannot generate a highly precise frequency, frequency precision of a VCO or a frequency synthesizer is provided by implementing feedback control using a phase locked loop (PLL) circuit so as to generate integer or fracture times the frequency of a quartz oscillator. However, a VCO using a quartz oscillator normally provides a frequency band around 5 to 30 MHz, and even the highest frequency band of approximately 100 MHz at most.
Requirements for a VCO used in a frequency synthesizer include a wide tunability of an oscillation frequency so as to cover enough frequency range, and a low phase noise characteristic, as well as compactness and low power consumption.
A phase noise is an index to characterize dispersion of an oscillation frequency. The lower phase noise indicates that the oscillation frequency is closer to a single frequency, that is, almost ideal. The phase noise of a VCO, through frequency conversion by a frequency mixer, adversely affects the spectrum of signals in transmitting and receiving. In an orthogonal frequency division multiplex (OFDM) system, which is used for a wireless LAN system, an asymmetrical digital subscriber line (ADSL), a digital terrestrial television and the like, the lower the phase noise of a VCO, the higher the quality of signals. Accordingly, in principle, the quantity of information for transmitting and receiving can be increased.
A phase noise is caused by a thermal noise, flicker noise (1/f noise) and the like, inside an oscillator circuit. The noises emerge, as a momentary shift in the oscillation frequency, at an output node of the oscillator circuit. In order to reduce a phase noise in an oscillator, it is effective to increase the quality factor (Q value) of a resonator used in an oscillator circuit.
As a resonator exhibiting a high Q value in an RF band of GHz frequency or more, a film bulk acoustic resonator (FBAR) has been proposed recently and has collected attention. Currently, as resonators used in RF communication systems, bulk (ceramic) dielectric resonators or surface acoustic wave (SAW) devices have been used. As compared with the currently used resonators, the FBAR is suitable for miniaturization, and also for higher frequency applications. On the basis of the above reasons, a high frequency filter using an FBAR has already been commercially manufactured. Moreover, there is a proposal to use an FBAR of an aluminum nitride (AlN) as a resonator of VCO (see A. P. S. Khanna, et al., “A 2 GHz Voltage Tunable FBAR Oscillator,” IEEE MTT Symposium Digest, pp. 717–720, 2003).
Moreover, there is a proposal in which, in order to achieve a wide oscillation frequency tunability, a detection circuit is added to detect the transition of an oscillating operation from an initial state into a steady state, and a load capacitance in a resonator is connected to improve tunability of the oscillation frequency. (refer to Japanese Patent Laid-Open No. 2002-344242).
Furthermore, there is another proposal employing a wide-band frequency synthesizer in a wireless communication system, in which a wide frequency tunability is realized by means of selecting a VCO from a plurality of VCOs having different frequency bands (refer to Japanese Patent Laid-Open No. 2002-314414).
The VCO disclosed in Japanese Patent Laid-Open No. 2002-344242 is a quartz oscillator and therefore inapplicable in a GHz frequency band. In addition, the VCO requires an additional detection circuit for an oscillation signal and, therefore, is not suitable for miniaturization. Moreover, according to A. P. S. Khanna, et al., a prototype of a VCO using an AlN FBAR with an oscillation frequency of 2 GHz has achieved an extremely low phase noise (C/N). However, only a value of approximately 0.1% can be achieved for a frequency tunability. Further, in Japanese Patent Laid-Open No. 2002-314414, the frequency synthesizer is constructed by using an LC oscillator having inductors and capacitors for a resonator. Therefore, the circuitry becomes large and phase noise reduction is difficult.
As described above, currently, a VCO using a FBAR which is suitable for miniaturization and capable to oscillate a frequency range over GHz has not yet reached a point of providing a needed frequency tunablilty. Therefore, there have been few disclosed frequency synthesizers with a VCO using a FBAR.
A first aspect of the present invention inheres in a voltage controlled oscillator, including a resonator configured to oscillate with an initial oscillation frequency during starting period of oscillation and with a steady oscillation frequency during a steady state oscillation, the resonator including a film bulk acoustic resonator having a series resonance frequency higher than the oscillation frequency; and a negative resistance circuit connected to the film bulk acoustic resonator, configured to drive the resonator, the negative resistance circuit having a positive increment for reactance in the steady state oscillation compared with reactance in the starting period.
A second aspect of the present invention inheres in a frequency synthesizer, including a voltage controlled oscillator including a plurality of film bulk acoustic resonators having different resonance frequencies, configured to generate an oscillation signal; a first frequency divider configured to divide the oscillation signal from the voltage controlled oscillator and to generate a divided oscillation signal; a second frequency divider configured to divide a reference signal and to generate a divided reference signal; a phase comparator configured to compare phases of the divided oscillation signal and the divided reference signal and to generate a phase error signal; a control voltage generator configured to generate a control voltage for the voltage controlled oscillator based on the phase error signal; and a control circuit configured to generate a control signal based on the control voltage so as to select the film bulk acoustic resonators, and to control an oscillation frequency of the oscillation signal.
A third aspect of the present invention inheres in a communication apparatus, including a frequency synthesizer configured to provide an oscillation signal, including: a voltage controlled oscillator including a plurality of film bulk acoustic resonators having different resonance frequencies, configured to generate the oscillation signal; a first frequency divider configured to divide the oscillation signal from the voltage controlled oscillator and to generate a divided oscillation signal; a second frequency divider configured to divide a reference signal and to generate a divided reference signal; a phase comparator configured to compare phases of the divided oscillation signal and the divided reference signal and to generate a phase error signal; a control voltage generator configured to generate a control voltage for the voltage controlled oscillator based on the phase error signal; and a control circuit configured to generate a control signal based on the control voltage so as to select the film bulk acoustic resonators, and to control an oscillation frequency of the oscillation signal; a receiver configured to convert a high frequency receiving signal into an intermediate frequency receiving signal by use of the oscillation signal; a baseband processor configured to demodulate the intermediate frequency receiving signal and to modulate a transmitting signal; and a transmitter configured to transmit a radio frequency transmitting signal provided by converting the modulated transmitting signal by use of the oscillation signal.
Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.
As shown in
The resonator 70 includes a reactance controller 52 connected to an input node 62, a phase adjuster 54 connected in series to the reactance controller 52, and a FBAR 56 connected in series to the phase adjuster 54. A control voltage source 66, which is grounded, is connected to the input node 62. Moreover, an output node 64 is provided at the other end of the negative resistance circuit 60 which is connected to the resonator 70 at the connection node 72, and a load 68 is connected to the output node 64.
As shown in
The bipolar transistors Q1 and Q2 construct a cascode circuit where the emitter of the transistor Q1 and the collector of the transistor Q2 are connected to each other. The transistor Q1 is a buffer transistor for driving the load, and the transistor Q2 serves as an oscillation transistor.
The DC power supply Vcc supplies a bias voltage to the transistors Q1 and Q2. The resistances R1 to R5 are bias resistances for determining operating points of the transistors Q1 and Q2. The inductor L1 connected between the DC power supply Vcc and the collector of the transistor Q1, and the grounded inductor L2 connected with the resistance R5 which is connected from the emitter of the transistor Q2, allow only direct-current components to pass therethrough and prevent high-frequency components from escaping into the DC power supply Vcc and the ground GND, respectively.
The capacitor C1 provides a high frequency wave oscillated by the transistor Q2 to the transistor Q1. The capacitor C2 grounds the collector of the transistor Q2 in a high frequency range. The capacitors C3 and C4 allow a signal, which emerges at the emitter of the transistor Q2 by amplifying a high frequency signal provided into the base of the transistor Q2, to feed back the signal again to the base of the transistor Q2 through the resonator 70. The capacitor C5 provides a high frequency signal from the collector of the transistor Q2 to the output node 64. In addition, the connection node 72 is connected to the resonator 70.
Note that, in the first embodiment, the bipolar transistor Q1 and Q2 are used in the negative resistance circuit 60. Although a field effect transistor (FET) or the like may be used instead of a bipolar transistor, it is desirable, in terms of noise reduction, to use the bipolar transistor which has a relatively low flicker noise. Further, a negative resistance circuit using a complementary metal oxide semiconductor (CMOS) inverter may be used.
The resonator 70 has a circuitry where the reactance controller 52, the phase adjuster 54 and the FBAR 56 are connected in series. The resonator 70 can be represented by an equivalent circuit model as shown in
In the reactance controller 52, which varies reactance depending on a control voltage Vcontrol applied from the control voltage source 66, a variable capacitance CVAR is used. The variable capacitances CVAR is provided by a variable capacitance diode using a pn junction of a semiconductor, a metal-oxide-semiconductor (MOS) capacitor, a high dielectric thin film capacitor which varies capacitance by using nonlinearity of a strontium titanate (SrTiO3) film or the like, an electrostatic capacitor having a variable gap between electrodes by using an electrostatic force, a piezoelectric property, and the like. One end of the capacitance CVAR is connected to an inductance LDC for removing high-frequency components included in the control voltage Vcontrol applied from the input node 62. The other end of the capacitance CVAR is grounded.
In the phase adjuster 54, an inductance LADJ, such as a microstrip line or a spiral inductor, is used. Note that it is desirable that the phase adjuster 54 has a structure which enables fine adjustment of phase characteristics of the resonator 70 by adjusting the inductance LADJ by laser trimming after the oscillator circuit is fabricated.
The FBAR 56 includes a piezoelectric thin film having a pair of electrodes on both sides and an acoustic reflector abutting on at least one of the pair of electrodes. The piezoelectric material includes an aluminum nitride (AlN), a zinc oxide (ZnO), a lead zirconate titanate (Pb(Zr,Ti)O3), a barium titanate (BaTiO3), and the like, or materials modified composition, for example, by adding another component thereto. The acoustic reflector is provided to enhance the Q value representing a resonance characteristic of the FBAR. The acoustic reflector may be a cavity, or may be a multilayer film for acoustic reflection. The resonance characteristic of the FBAR 56 can be appreciably precisely expressed by using the equivalent circuit shown in
In the first embodiment, an initial oscillation angular frequency ωstart immediately after the introduction of power into the VCO 50, is designed to be between a series resonance angular frequency ωs and a parallel resonance angular frequency ωp of the FBAR 56 so as to stably start the oscillation. Then, a steady oscillation angular frequency ωosc, after amplitude of the oscillation settles into a state of saturation, is designed to be lower than the series resonance angular frequency ωs by using the nonlinearity of the negative resistance circuit 60. If the VCO 50 is thus designed, the frequency tunability of the VCO 50 can be increased as described below.
The impedance characteristic of the FBAR 56 around the resonance frequency can be generally described as follows. In an angular frequency range lower than the series resonance angular frequency ωs of the FBAR 56 and an angular frequency range higher than the parallel resonance angular frequency ωp of the FBAR 56, a reactance XFBAR=Im(ZFBAR) of the FBAR 56 is a negative value and the FBAR 56 behaves like a capacitor. On the other hand, in a limited frequency range from the series resonance angular frequency ωs to the parallel resonance angular frequency ωp, the reactance XFBAR is a positive value and the FBAR 56 behaves like an inductor. At the series resonance angular frequency ωs, a real part RFBAR=Re(ZFBAR) of a complex impedance of the FBAR 56 is a relatively small value. By contrast, the RFBAR is the largest at the parallel resonance angular frequency ωp.
It is usual, for an oscillator circuit using piezoelectric resonator, in order to achieve stable oscillating operation, that the circuit is designed so as to oscillate in a frequency range where a piezoelectric resonator behaves like an inductor, that is, between the series resonance angular frequency ωs and the parallel resonance angular frequency ωp. Accordingly, in the oscillator circuitry providing an oscillation in the frequency range where the piezoelectric resonator behaves like an inductor, an only narrow frequency tunability may be realized.
To the contrast, according to the first embodiment, as will be described below, the initial oscillation angular frequency ωstart, which is 2*π*fstart, immediately after the introduction of power into the VCO 50 is designed such that the initial oscillation frequency is between the series resonance angular frequency ωs and the parallel resonance angular frequency ωp. However, the steady oscillation angular frequency ωosc, which is 2*π*fosc, after amplitude of the oscillation settles into a state of saturation, is designed to be lower than the series resonance angular frequency ωs. Thus, the frequency tunability of the VCO 50 may increase.
Using equivalent circuit parameters, the series resonance angular frequency ωs and the parallel resonance angular frequency ωp of the FBAR 56 can be expressed by the following equations.
ωs=2*π*fs=[1/(LF*CF1)]1/2 (1)
ωp=2*π*fp=[(1/CF1+1/CF0)/LF]1/2 (2)
Moreover, using the equivalent circuit parameters, the complex impedance ZFBAR of the FBAR 56 with respect to an angular frequency ω can be expressed by the following equation:
ZFBAR=1/(j*ω*CF0)+1/((ω*CF0)2/{RF+j*[*LF−(1/CF1+1/CF0)/ω]} (3)
where the first term in the right-hand side of the equation (3) relates to an electrostatic capacitance CF0 of the FBAR 56, and the second term relates to a acoustic piezoelectric vibration of the FBAR 56.
Here, an antiresonance resistance RA and a phase angle θ are defined as follows.
RA=1/(ω2*CF0*RF) (4)
tan θ=[ω*LF−(1/CF1+1/CF0)/ω]/RF (5)
−π/2<θ<π/2 (6)
Using the antiresonance resistance RA and the phase angle θ, the complex impedance ZFBAR can be expressed as follows.
The VCO 50 shown in
Referring to
ZRES=ZFBAR+j*[LADJ−1/(ω*CVAR)] (8)
Accordingly, it is understood that the variable capacitance CVAR and the inductance LADJ are circuit elements for adding or subtracting to the imaginary component, that is, the reactance component XFBAR, of the complex impedance of the FBAR 56. Strictly speaking, ω*LADJ or 1/(ω*CVAR) is also a function relating to the frequency. However, each of ω*LADJ and 1/(ω*CVAR) can be thought to be an approximately constant value in the narrow resonance frequency range in comparison with the reactance component XFBAR of the FBAR 56 sharply increasing or decreasing around the resonance frequency.
Moreover, as shown in
As for a variation of the complex impedance with respect to the oscillation amplitude, since the complex impedance ZRES of the resonator 70 is provided by impedances of passive elements, the complex impedance ZRES can be thought to be approximately constant even if the oscillation amplitude varies. On the other hand, since the complex impedance ZNEG of the negative resistance circuit 60 includes the transistors which are active elements, the complex impedance ZNEG, reflecting the nonlinearity of the transistors, is a function varying values according to the magnitude of the oscillation amplitude.
The complex impedance ZNEG of the negative resistance circuit 60 cannot be expressed by a simple expression like the equation (8) because the negative resistance circuit 60 is a nonlinear circuit including the transistors. However, by use of a large signal nonlinear transistor model, such as a Gummel-Poon model, and model parameters having experimentally sufficient precision, it is possible to precisely predict the complex impedance ZNEG by circuit simulation. Note that, for designing the negative resistance circuit 60 which operates at a high frequency, it is necessary to sufficiently consider parasitic components of individual parts other than the parameters including parasitic components concerning the above-discussed transistors so that the impedance characteristics correspond in the oscillation frequency band. Moreover, it is necessary to use a circuit where consideration has been previously provided to parasitic components of circuit wirings connecting one part to another.
As shown in
Since the oscillation amplitude is extremely small immediately after the oscillation has started, a condition for small signal operation of a transistor applies. In general, in order to decrease the duration from the time of turning on the power until steady state oscillating, it is desirable to set a loop gain of the negative resistance circuit 60 for the small signal operation to 3 or more. Here, the frequency ωstart that satisfies a phase condition during the small signal operation, during the activation duration of the oscillation, is to be in the frequency range between the series resonance angular frequency ωs and the parallel resonance angular frequency ωp of the FBAR 56. Once the oscillation starts, due to a loop gain of greater than one of the negative resistance circuit 60, the oscillation is amplified during the amplification duration and the oscillation amplitude accordingly increases. When the oscillation amplitude increases, due to the nonlinearity of the transistors, the loop gain gradually decreases to one. Consequently, the oscillation is close to steady state. Thus, intentionally using the nonlinearity of the transistors in the negative resistance circuit 60, the frequency that satisfies the phase condition in the steady state may be lower than the series resonance angular frequency ωs of the FBAR 56.
First, the activation duration when the VCO 50 starts to oscillate is considered. During the activation duration, a small signal source, such as a weak noise voltage/current existing in the circuit, and a minute harmonic component caused by the transient phenomena at the time of turning on power, is selectively amplified. Therefore, an oscillation condition to be determined can be analyzed, using parameters of a small signal linear circuit. The oscillation start conditions of an oscillation circuit can be represented by the following expressions, respectively relating to resistance components R in the complex impedances of the resonator 70 and the negative resistance circuit 60, and the reactance components X thereof.
RRES≦−RNEG(Asmall) (9)
XRES=−XNEG(Asmall) (10)
Here, Asmall is a small signal oscillation amplitude.
As for the oscillation start condition, that is a gain condition, relating to the resistance components R in the complex impedances in the expression (9), the impedance of the FBAR 56 may decrease by increasing the area of the FBAR 56 to a certain level or more so that the transistors included in the negative resistance circuit 60 can be driven. Therefore, for the oscillation start condition, it is sufficient to mainly consider the phase condition relating to the reactance components X in the equation (10).
The equation (10), which represents the phase condition of the resonator 70, can be transformed into the following equation:
XFBAR((ωstart)+XVAR(ωstart)+XADJ((ωstart)=−XNEG(Asmall, ωstart) (11)
where XVAR(ωstart) is the reactance of the reactance controller 52, and XADJ(ωstart) is the reactance of the phase adjuster 54. Accordingly, the reactance XFBAR(ωstart) of the FBAR 56 can be expressed as follows.
XFBAR(ωstart)=−XNEG(Asmall, ωstart)−XVAR(ωstart)−XADJ(ωstart) (12)
The value of the reactance XFBAR(ωstart) is a positive value between the series resonance and parallel resonance of the FBAR 56, and the FBAR 56 behaves as an inductor. Consequently, a condition which makes the value of {−XNEG(Asmall, ωstart)−XVAR(ωstart)−XADJ(ωstart)} a positive value, as expressed by the following inequality, provides the oscillation to start between the series resonance and the parallel resonance.
XNEG(Asmall, ωstart)+XVAR(ωstart)+XADJ(ωstart)<0 (13)
Next, the case where the oscillation amplitude has been gradually increased and settles in the steady state as shown in
The active elements, such as the transistors, included in the negative resistance circuit 60 linearly operate during the small signal operation. However, the active elements may nonlinearly operate when the signals become large. During the large signal operation, an average complex impedance ZNEG(Aosc) generally exhibits a different value from the complex impedance ZNEG(Asmall) during the small signal operation. A difference between the reactance component XNEG(Aosc) of the negative resistance circuit 60 around the resonance frequency during the large signal operation and the reactance component XNEG(Asmall) during the small signal operation is denoted by ΔXNEG. Note that the term “Aosc” is a large signal oscillation amplitude. In other words, the difference ΔXNEG means a difference between the reactances of the negative resistance circuit 60 during the large signal operation and during the small signal operation.
If the VCO 50 can be designed such that the value of {XNEG(Asmall, ωstart)+XVAR(ωstart)+XADJ(ωstart)} during the small signal operation is negative and the value of {XNEG(Aosc, ωosc)+ΔXNEG+XVAR(ωosc)+XADJ(ωosc)} during the large signal operation in the steady state is positive, the VCO 50 may start to oscillate at a frequency fstart between a series resonance frequency fs and a parallel resonance frequency fp of the FBAR 56. Further, the oscillation frequency is gradually reduced as the oscillation amplitude is increased, and the VCO 50 may steadily oscillate at a frequency fosc that is lower than the series resonance frequency fs.
Next, a description will be given of how a reactance component in a circuit can be varied between at starting of oscillation and during a steady state oscillation. Note that a difference between oscillation frequencies at the staring of oscillation and during the steady state is small in comparison with a value of the oscillation frequency of a negative resistance circuit. Therefore, the difference between the oscillation frequencies will be ignored in the following description.
Here, it is assumed that only the transconductance gm is varied depending on voltage amplitude. That is, it is assumed that the large transconductance gm is determined when the amplitude of an input voltage ν is sufficiently small, but the transconductance gm gradually decreases as the voltage amplitude increases because the transistor may be saturated. An examination will be made of what influence such a variation of the transconductance gm has on the impedance Zneg of the negative resistance circuit in
Next, an examination will be made of a case where, as shown in
Next, an examination will be made of a case where, as shown in
Assuming that a piezoelectric resonator is connected to the negative resistance circuit and the above-discussed phase adjusting means, when the transconductance gm is large at the start of oscillation, the negative resistance circuit oscillates with a positive reactance component of the piezoelectric resonator, that is, in a frequency range between the series resonance frequency and the parallel resonance frequency. Moreover, when the transconductance gm is small in steady state oscillation, the negative resistance circuit oscillates with a negative reactance component of the piezoelectric resonator, that is, below the series resonance frequency.
Note that the variable capacitance Cvar of the reactance controller 52 has been ignored for simplification in the foregoing description. However, even when the variable capacitance Cvar is present, the variable capacitance Cvar only has an influence of relatively varying the value of the reactance. Therefore, the case where the variable capacitance Cvar is present also conforms to the foregoing description qualitatively.
The foregoing description has been given using the simplest model where only the minimum parasitic component of transistors is considered in the negative resistance circuit. Therefore, it is necessary in practice to consider other various parasitic components. Accordingly, when designing the VCO 50, it is necessary to adjust circuit parameters using a more precise transistor model and a circuit simulator so as to satisfy the following equation relating to steady state oscillation at an angular frequency lower than the series resonance angular frequency ωs of the FBAR 56 alone.
ZNEG(Aosc, ωosc)+ZRES(ωosc)=0. (14)
At a frequency equal to a series resonance frequency fs or lower, the reactance XFBAR(ωosc) of the FBAR 56 provides a negative value. However, the reactance XFBAR(ωosc) is greater than a value of reactance {−1/(ωs·CF0)} attributable to the electrostatic capacity CF0. Therefore, in order to achieve steady state oscillation, by focusing attention on large signal reactance of circuitry elements other than the FBAR 56, a circuit of the resonator may be constructed such that the following inequality is satisfied for the series resonance angular frequency ω0, of the FBAR 56.
0<XVAR(ωs)+XADJ(ωs)+XNEG(Aosc, ωs)<1/(ωs·CF0) (15)
Here, for the value of each of the reactance components XVAR(ωs) XADJ(ωs), and XNEG(Aosc, ωs), it is necessary to consider parasitic components involved in packaging of respective circuitry elements and circuit wirings. For the negative resistance circuit 60, in particular, it is necessary to predict the parasitic components with high precision simulation of a high frequency circuit, using a large amplitude model capable of precisely representing the value of the reactance XNEG(Aosc, ωs) as well as the nonlinearity of the transistor.
Moreover, in the inequality (15), the reactance XVAR(ωs) of the reactance controller 52 always presents a negative value. In addition, the reactance XNEG(Aosc, ωs) of the negative resistance circuit 60 also often presents a negative value. In such case, in order to satisfy the inequality (15), reactance of the resonator 70 is adjusted using a reactance XADJ(ωs) of a positive value of the phase adjuster 54.
In the resonator 70, it is assumed that, the reactance XVAR(ωs) of the reactance controller 52 on the series resonance angular frequency ωs of the FBAR 56, varies with a maximum of ΔXVAR within a voltage variable range of the control voltage Vcontrol of the control voltage source 66. It is also assumed that the reactance XRES(ωs) of the resonator 70 is accordingly varied with a maximum of ΔXVAR, which causes a variation in the phase condition for oscillation and thus causes a variation of Δfosc in the oscillation frequency. Assuming that, around the series resonance frequency fs of the FBAR 56, each of the reactances XNEG(Aosc, ωs) and XADJ(ωs) of the negative resistance circuit 60 and the phase adjuster 54, respectively, can be approximated to a substantially constant value. Then, the variation Δfosc in the oscillation frequency can be approximately expressed by the following equation.
Δfsc=(∂f/∂XRES)*ΔXRES≈(∂XFBAR/∂f)−1*ΔXVAR (16)
When focusing attention on a frequency around the series resonance frequency fs which allows the resistance components RFBAR of the complex impedance of the FBAR 56 to provide a small value, the gradient of the reactance XFBAR of the FBAR 56 with respect to the frequency is high when the frequency is higher than the series resonance frequency fs. Accordingly, the value of (∂XFBAR/∂f)−1 in the right hand side of the equation (16) is small. More specifically, only a small variation Δfosc in the oscillation frequency can be determined for a reactance difference ΔXVAR of the reactance controller 52.
On the other hand, when the oscillation frequency is lower than the series resonance frequency fs, the gradient of the reactance XFBAR of the FBAR 56 with respect to the frequency is low. Accordingly, the value (∂XFBAR/∂f)−1 in the right hand side of the equation (16) provides a relatively large value. Therefore, a large variation Δfosc in the oscillation frequency can be determined for the reactance difference ΔXVAR of the reactance controller 52.
In principle, the operation of the VCO 50 has a characteristic that only a frequency that satisfies the oscillation condition at small signals is selectively amplified. The first embodiment is characterized in that the oscillation start condition is limited to an extremely narrow frequency range between the series resonance and parallel resonance of the FBAR 56. Such characteristic has the effect of suppressing abnormal oscillation at an undesired frequency. Accordingly, stable oscillation can be achieved. Moreover, in the steady state where the oscillation amplitude is sufficiently amplified, the oscillation frequency fosc may vary in a wide frequency range by varying the oscillation frequency fosc to a frequency lower than the series resonance frequency fs.
When a reactance attributable to the electrostatic capacity CF0 of the FBAR 56 at the series resonance angular frequency ωs is defined as XFBAR0, the XFBAR0 can be represented as follows.
XFBAR0=−1/(ωs*CF0) (17)
In addition, a reactance at a center value of the control voltage Vcontrol for the reactance controller 52 at the series resonance angular frequency ωs is defined as XVAR0. For example, it has been confirmed that a wide frequency tunability of approximately 1% or more can be assured by designing an area S of the FBAR 56 such that a value of a reactance ratio XVAR0/XFBAR0 is 0.30 or larger. When the value of the reactance ratio XVAR0/XFBAR0 is 1.50 or larger, the VCO 50 cannot oscillate in the entire control voltage range. Therefore, it is desirable that the value of the reactance ratio XVAR0/XFBAR0 is in a range of not less than 0.30 and not more than 1.50.
Furthermore, a difference between a maximum value XFBARMax and a minimum value XFBARMin of the reactance around the resonance frequency of the FBAR 56 is defined as follows.
ΔXFBAR=XFBARMax−XFBARMin (18)
For example, around the resonance frequency of the FBAR 56, by converting a scattering (S) parameter measured by a network analyzer into a complex impedance, the difference ΔXFBAR can be provided. When the complex impedance ZFBAR around the series resonance frequency fs of the FBAR 56 is plotted on a complex plane (RFBAR, jXFBAR), an impedance circle can be drawn. Approximately, the difference ΔXFBAR corresponds to the diameter of the impedance circle. The diameter of the impedance circle is reduced in substantially inverse proportion to an area S of opposing electrodes of the FBAR 56.
Similarly, when the high frequency characteristic around the resonance frequency of the FBAR 56 is measured by varying the control voltage Vcontrol applied to the reactance controller 52, it is possible to measure a maximum reactance difference ΔXVAR within the control voltage variable range around the oscillation frequency of the reactance controller 52. For example, when the reactance controller 52 is a variable capacitance diode, the maximum reactance difference can be approximately expressed by the following expression,
ΔXVAR>>|1/CVARMax−1/CVARMin|(2 *π*fs) (19)
Here, CVARMax is a maximum capacitance and CVARMin is a minimum capacitance in the control voltage range.
In the VCO 50 using the FBAR 56, the value of the ratio ΔXVAR/ΔXFBAR between the maximum reactance difference ΔXVAR of the reactance controller 52 and the reactance difference ΔXFBAR of the FBAR 56 is important. The larger the value of the ratio ΔXVAR/ΔXFBAR, the wider the frequency tunability. For example, since the variable capacitance diode as the reactance controller 52 uses a variation of pn junction capacitance, it is difficult to obtain more than a certain fixed value of a reactance difference ΔXVAR within the limited control voltage range. In such case, it is possible to obtain the value of the ratio ΔXVAR/ΔXFBAR by enlarging the area S of the FBAR 56.
Specifically, it has been confirmed that a wide frequency tunability of approximately 1% or more can be assured by designing the area S of the FBAR 56 such that the value of the ratio ΔXVAR/ΔXFBAR is 0.05 or larger. When the value of the ratio ΔXVAR/ΔXFBAR is 0.30 or larger, the VCO 50 cannot oscillate in the entire control voltage range. Therefore, it is desirable that the value of the ratio ≢XVAR/ΔXFBAR is in a range of not less than 0.05 and not more than 0.30.
As described above, according to the first embodiment, the initial oscillation angular frequency ωstart immediately after turning on power to the VCO 50 enables oscillation to start stably between the series resonance angular frequency ωs and the parallel resonance angular frequency ωp of the FBAR 56. Moreover, the oscillation angular frequency ωosc after the oscillation settles into the steady state may be lower than the series resonance angular frequency ωs by using the nonlinearity of the negative resistance circuit 60, which makes it possible to increase the frequency tunability of the VCO 50.
Next, an example of the VCO 50 according to the first embodiment will be described. For a piezoelectric thin film of the FBAR 56, for example, AlN is used. An opposing electrode area of the FBAR 56 is 10000 μm2. Values of equivalent circuit parameters of the FBAR 56 are calculated by fitting so that the values are best matched with a measurement result of the resonance characteristic of the FBAR 56.
As shown in
Moreover, the frequency characteristics of the resistance component (−RNEG) and the reactance component (−XNEG) of the negative resistance circuit 60 also shown in
From
Moreover, from
Next, after the oscillation has started, the VCO 50 settles into the steady state. As shown in
The reason why the oscillation frequency varies from the initial oscillation frequency fstart to the steady oscillation frequency fosc is that, as stated above, the values of the small signal operation reactance {−XNEG(Asmall)} and the large signal operation reactance {−XNEG(Aosc)} vary due to the nonlinearity of the transistors included in the negative resistance circuit 60. An example can be found in which the phenomenon that the initial oscillation frequency fstart and the steady oscillation frequency fosc, vary as described above has been observed in an oscillator other than the VCO 50 using the FBAR 56 (refer to Kazuhiko Honjo, “Microwave semiconductor circuit—fundamentals and developments,” published by Nikkan Kogyo Shimbun, p. 170 (1993)). However, there have been no reported examples concerning a VCO using an FBAR. Further, in the VCO 50 using the FBAR 56, oscillation is normally implemented in a frequency range where the reactance XFBAR of the FBAR 56 is a positive value to be assumed as an inductance. In other words, oscillation is implemented in a frequency range from the series resonance frequency fs to the parallel resonance frequency fp of the FBAR 56. No example is found in which oscillation is stably implemented in a frequency outside the frequency range between the series resonance frequency fs and the parallel resonance frequency fp.
As a comparative example, in order to provide steady oscillation in the frequency range between the series resonance frequency fs and the parallel resonance frequency fp of the FBAR 56, a VCO circuit is designed with a similar circuitry of the VCO 50 so that large signal reactances of circuitry elements other than the FBAR 56 satisfy the following inequality,
XaVAR(ωs)+XaADJ(ωs)+XaNEG(Aosc, ωs)<0. (20)
Here, XaVAR(ωs) is a reactance of a reactance controller, XaADJ(ωs) is a reactance of a phase adjuster, and XaNEG(Aosc, ωs) is a reactance of the negative resistance circuit 60 during the steady oscillation.
In the first embodiment, as shown in
As shown in
As described above, the VCO 50 using the FBAR 56 according to the first embodiment can provide low phase noise and assures a sufficiently wide frequency tunability because of the high Q value of the FBAR 56 at resonance. Accordingly, a communication apparatus having the VCO 50 using the FBAR 56 as a local oscillator can transmit high quality information in bulk.
Note that, in the first embodiment, a variable capacitance diode or the like, is used for the reactance controller 52. Since the variable capacitance diode and the FBAR 56 are both capacitive elements, the reactance is inversely proportional to the electrostatic capacity CFO. Therefore,
The reactance XVAR of the reactance controller 52 varies with the control voltage Vcontrol. When the voltage variable range of the control voltage Vcontrol is set from 0.6 V to 2.1 V, as shown in
The value of the reactance difference ΔXFBAR of the FBAR 56 shown in
In
As described above, it is possible to vary the oscillation frequency band of the VCO by varying the electrode area S of the FBAR 56. However, the oscillation frequency band of the VCO can be also varied by varying thickness of the piezoelectric thin film of the FBAR 56. The series resonance frequency fs and the parallel resonance frequency fp of the FBAR 56 are determined depending on a time period taken for a sound to travel in the piezoelectric thin film between the electrodes of the FBAR 56. When the thickness of the piezoelectric thin film is increased by, for example, 10%, both the series resonance frequency fs and the parallel resonance frequency of the FBAR 56 decrease by approximately 10%. On the contrary, when the thickness of the piezoelectric thin film decreases, the series resonance frequency fs and the parallel resonance frequency of the FBAR 56 increase substantially in direct proportion to the thickness of the piezoelectric thin film. Accordingly, it is possible to vary the oscillation frequency band of the VCO by varying the thickness of the piezoelectric thin film of the FBAR 56 and thereby varying the series resonance frequency fs of the FBAR 56.
As shown in
The negative resistance circuit 60a includes a CMOS inverter 80, a feedback resistance Rfb connected to an input and an output of the CMOS inverter 80, a load capacitance CL1 connected to the input side of the CMOS inverter 80, and a load capacitance CL2 connected to the output thereof. The load capacities CL1 and CL2 are grounded. The output of the CMOS inverter 80 is connected to the output node 64 of the VCO 50a.
The FBAR 56 in the resonator 70a is connected to a node 74 between the load capacity CL2 on the output of the CMOS inverter 80 and the output node 64. The phase adjuster 54, connected to the FBAR 56, is connected to the reactance controller 52a with a node 78 interposed therebetween. The reactance controller 52a is connected to the input node 62 to which a control voltage for reactance control is applied. Moreover, the reactance controller 52a is connected to the input of the CMOS inverter 80, to which the feedback resistance Rfb and the load capacity CL1 are connected, with a node 76 interposed therebetween.
The VCO 50a according to the first modification of the first embodiment is different from the VCO according to the first embodiment in that the CMOS inverter 80 is used as the negative resistance circuit 60a. The other configurations are similar to the first embodiment. Therefore, redundant descriptions will be omitted.
As shown in
The DC cut capacitance CCUT and the high frequency signal blocking inductance LC, both connected to the variable capacitance CVAR, are unnecessary components in the resonator 70a. Therefore, in order not to affect the oscillation conditions of VCO 50a, the values of the DC cut capacitance CCUT and the high frequency signal blocking inductance LC are designed larger so that the DC cut capacitance CCUT and the high frequency signal blocking inductance LC can be ignored with respect to the reactance of the series connection of the FBAR 56, the phase adjuster 54 and the reactance controller 52a. For example, it is sufficient that the value of the DC cut capacitance CCUT is at least one order of magnitude greater than the value of the variable capacitance CVAR, and that the high frequency signal blocking inductance LC is at least one order of magnitude greater than the inductance LADJ in the phase adjuster 54.
Accordingly, a circuit equivalent to the resonator 70a may be substantially the same as that shown in
The CMOS inverter 80 in the negative resistance circuit 60a provides nonlinearity in the large amplitude steady state. Therefore, circuit parameters for the CMOS inverter 80 and the resonator 70a are determined by simulation. Thus, it is possible to determine the complex impedances ZRES and ZNEG of the resonator 70a and the negative resistance circuit 60a, respectively, which satisfy the oscillation start conditions at small signals represented by the expressions (9) and (10) and the steady oscillation condition represented by the equation (14).
As described above, according to the first modification of the first embodiment, it is possible to stably start oscillation by satisfying the inequality (13) immediately after turning on power to the VCO 50a and thereby allowing the initial oscillation angular frequency ωstart between the series resonance angular frequency ωs and the parallel resonance angular frequency ωp of the FBAR 56. In the steady state after the oscillation has started, it is possible to achieve the steady oscillation angular frequency ωosc lower than the series resonance angular frequency ωs by satisfying the inequality (15) utilizing the nonlinearity of the negative resistance circuit 60a. Thus, it is possible to increase the frequency tunability of the VCO 50a.
In addition, the CMOS inverter 80 in the negative resistance circuit 60a is desirable for integration and manufacturing in comparison with a bipolar transistor and therefore advantageous in reducing the size and costs of the VCO 50a. Further, the development of a high frequency CMOS analog circuit is in progress, and thus merged installation of a high frequency analog circuit and a digital circuit will be facilitated.
As shown in
The negative resistance circuit 60b includes a CMOS inverter 80 and a feedback resistance Rfb connected to an input and an output of the CMOS inverter 80. The output of the CMOS inverter 80 is connected to an output node 64 of the VCO 50b.
The FBAR 56 in the resonator 70b is connected between the output of the CMOS inverter 80 and the output node 64. The phase adjuster 54, connected to the FBAR 56, is connected between the input of the CMOS inverter 80 and the feedback resistance Rfb. The reactance controller 52b includes first and second variable capacitances CVAR1 and CVAR2 which are variable capacitance diodes or the like. The first variable capacitance CVAR1 is connected between the output of the CMOS inverter 80 and the output node 64 to the FBAR 56, with a DC cut capacitance CCUT1 interposed therebetween. An input node 62a, to which control voltage for reactance control is applied and is connected between the first variable capacitance CVAR1 and the DC cut capacitance CCUT1, with an inductance LDC1 removing a high frequency component interposed therebetween. Moreover, the second variable capacitance CVAR2 is connected between the input of the CMOS inverter 80 and the feedback resistance Rfb to the phase adjuster 54, with a DC cut capacitance CCUT2 interposed therebetween. An input node 62b, to which control voltage for reactance control is applied, is connected between the second variable capacitance CVAR2 and the DC cut capacitance CCUT2, with an inductance LDC2 removing a high frequency component interposed therebetween.
Although the first and second variable capacitances CVAR1 and CVAR2 of the reactance controller 52b are provided in the resonator 70b, the first and second variable capacitances CVAR1 and CVAR2 also serve as load capacitances of the CMOS inverter 80 in the negative resistance circuit 60b. Thus, the circuitry of the negative resistance circuit 60b can be simplified. Note that values of the DC cut capacitances CCUT1 and CCUT2 are at least one order of magnitude greater than the first and second variable capacitance CVAR 1 and CVAR2, and therefore can be ignored as reactance.
The second modification of the first embodiment is different from the first modification of the first embodiment in that the first and second variable capacitances CVAR1 and CVAR2 are provided for the reactance controller 52b in the resonator 70b and also serve as the load capacitances of the CMOS inverter 80 in the negative resistance circuit 60b. The other configurations are substantially the same as the first modification of the first embodiment. Therefore, redundant descriptions will be omitted.
Unlike the complex impedances in the first embodiment and the first modification of the first embodiment, the complex impedance of the resonator 70b shown in
ZbRES=ZFBAR+ZADJ (21)
ZbNEG=1/{1/ZNEG+1/(2*ZVAR)}=RbNEG+j*XbNEG (22)
Here, the complex impedance ZbNEG of the negative resistance circuit 60b is equivalent to a parallel connection of a component ZNEG attributable to the CMOS inverter 80 and a composite component of (2*ZVAR) in a series connection of the first and second variable capacitances CVAR1 and CVAR2, which results in the complicated expression. However, by mathematically arranging the expression, the expression can be finally expressed using a resistance RbNEG and a reactance XbNEG.
In such case, corresponding to the inequality (13), an expression to satisfy the oscillation start condition of the VCO 50b can be expressed as follows.
XbNEG(Asmall, ωosc)+XADJ(ωosc)<0 (23)
Moreover, corresponding to the expressions (14) and (15) expressions to satisfy the steady oscillation condition are expressed as follow.
ZbNEG(Aosc, ωosc)+ZbRES(ωosc)=0 (24)
0<XADJ(ωs)+XbNEG(Aosc, ωs)<1/( 7s*CF0) (25)
As described above, according to the second modification of the first embodiment, it is possible to stably start oscillation by satisfying the inequality (23) immediately after turning on power to the VCO 50b and thereby allowing the initial oscillation angular frequency ωstart between the series resonance angular frequency ωs and the parallel resonance angular frequency ωp of the FBAR 56. In the steady state after the oscillation has started, it is possible to allow the steady oscillation angular frequency ωosc lower than the series resonance angular frequency by satisfying the inequality (25) utilizing the nonlinearity of the negative resistance circuit 60b. Thus, it is possible to increase the frequency tunability of the VCO 50b.
In addition, the CMOS inverter 80 in the negative resistance circuit 60b is desirable for integration and manufacturing in comparison with a bipolar transistor. Further, the CMOS inverter 80 is advantageous in reducing the size and cost of the VCO 50b. Furthermore, since the first and second variable capacitances CVAR1 and CVAR2 in the reactance controller 52b are used as the load capacities of the CMOS inverter 80, it is possible to simplify the circuitry of the negative resistance circuit 60b.
As shown in
The PLL circuit 99 includes first to fourth VCOs 51a to 51d having inputs connecting with each other, to which the control voltage Vcontrol for resonators in the respective VCOs is applied. The first to fourth VCOs 51a to 51d are connected to an output node 64 and to an input of a first frequency divider 82 via switches SW1 to SW4, respectively, which are connected to outputs of the respective VCOs. Outputs of the first frequency divider 82 and a second frequency divider 84 connected to a reference signal source 86 are connected to an input of a phase comparator 88. Moreover, a lock detector 90 is connected to the phase comparator 88. An input and an output of a control voltage generator 91 are respectively connected to the output of the phase comparator 88, and to the inputs of the first and second voltage comparators 96 and 98. The output of the control voltage generator 91 is also connected to the inputs of the first to fourth VCOs 51a to 51d. The control voltage generator 91 has a charge pump 92 on the input portion and a loop filter 94 on the output portion.
The first and second comparison potentials Vcomp1 and Vcomp2 are applied to the first and second voltage comparators 96 and 98, respectively, to which the output of the control voltage generator 91 is connected. Here, the first and second comparison potentials Vcomp1 and Vcomp2 correspond to the lower and upper limit potentials of the control voltage generated by the control voltage generator 91, respectively. The outputs of the first and second voltage comparators 96 and 98 are connected to the control circuit 100. Moreover, outputs of the control circuit 100 generating the control signals SGC1 to SGC4 are respectively connected to the switches SW1 to SW4 of the first to fourth VCOs 51a to 51d.
The first to fourth VCOs 51a to 51d are designed such that the respective oscillation frequencies are variable in different frequency bands from one another, using FBARs having different film thicknesses. A circuitry inside the first to fourth VCOs 51a to 51d is similar to that of the VCO 50 in the first embodiment. Therefore, redundant descriptions will be omitted.
As shown in
The first to fourth VCOs 51a to 51d are switched in order from the first VCO 51a to the fourth VCO 51d, or reversely in order from the fourth VCO 51d to the first VCO 51a, using the switches SW1 to SW4 which are switched by the control signals SGC1 to SGC4 from the control circuit 100 to be described later. Thus, it is possible for the frequency synthesizer to operate in a wide oscillation frequency band from f1Min to f4Max.
The first frequency divider 82 in the PLL circuit 99 divides an oscillation signal SHF which is oscillated by the first to fourth VCOs 51a to 51d and selected using the switches SW1 to SW4. The second frequency divider 84 sets a dividing ratio based on frequency data provided by an external circuit (not shown) and divides a reference signal SREF from the reference signal source 86. For example, the oscillation signal SHF provided by one of the first to fourth VCOs 51a to 51d is in a GHz band. On the other hand, the reference signal SREF provided by the oscillation of, for example, a quartz oscillator or the like is in a band from approximately 5 MHz to 40 MHz. Particularly, a band from 16 MHz to 32 MHz is used for communication. Therefore, the dividing ratio used in the first frequency divider 82 is set to a magnitude of a single digit greater than that used in the second frequency divider 84. Moreover, the first frequency divider 82 is set such that the dividing ratio thereof is altered depending on the frequency data of the reference signal source 86 when the frequency data are altered.
The phase comparator 88 compares a phase of a divided oscillation signal DF1, which is divided by the first frequency divider 82, with a phase of a divided reference signal DF2, which is divided by the second frequency divider 84. The charge pump 92 in the control voltage generator 91 implements time integration for a phase error signal ΔDF which is generated as a result of the comparison of the phases of the divided oscillation signal DF1 and the divided reference signal DF2 by the phase comparator 88. The charge pump 92 then generates a phase error integrated signal SDF having a magnitude corresponding to the phase error signal ΔDF. The loop filter 94 in the control voltage generator 91 converts the phase error integrated signal SDF into a DC voltage and thus generates the control voltage Vcontrol. The charge pump 92 and the loop filter 94 are designed based on a phase lock technology and enable the reference signal SREF and the oscillation signal SHF to synchronize with each other within a predetermined period of time. Based on the phase error signal ΔDF from the phase comparator 88, the lock detector 90 detects whether the PLL circuit 99 is in an unlock condition or in a lock condition. When detecting the lock condition, the lock detector 90 locks the PLL circuit 99.
The first and second voltage comparators 96 and 98 have the first and second comparison potentials Vcomp1 and Vcomp2, respectively, which are lower and upper limit potentials, respectively. The first and second voltage comparators 96 and 98 monitor whether the control voltage Vcontrol is within a range between the first and second comparison potentials Vcomp1 and Vcomp2 Specifically, when the control voltage Vcontrol is lower than the first comparison potential Vcomp1, the first voltage comparator 96 generates an output signal VC1. When the control voltage Vcontrol is higher than the second comparison potential Vcomp2, the second voltage comparator 98 generates an output signal VC2.
The control circuit 100 generates any one of the control signals SGC1 to SGC4 in response to the output signal VC1 or VC2 from the first or second voltage comparator 96 or 98, so as to turn on any one of the switches SW1 to SW4. When neither of the output signals VC1 nor VC2 is received, the control circuit 100 retains any one of the control signals SGC1 to SGC4 which is last generated.
Next, a description will be given of the operation of the frequency synthesizer according to the second embodiment. When turning on power, the control circuit 100 generates as an initial value, for example, a control signal SGC1 to select the first VCO 51a. The control signal SGC1 turns on the switch SW1. The other control signals SGC2 to SGC4 are not provided, and therefore the switches SW2 to SW4 are off. Accordingly, the oscillation signal SHF having the oscillation frequency of the first VCO 51a is divided by the first frequency divider 82, and a divided oscillation signal DF1 is sent to the phase comparator 88.
The reference signal SREF is divided by the second frequency divider 84, and the divided reference signal DF2 is added to the phase comparator 88.
In the phase comparator 88, the phases of the divided oscillation signal DF1 and the divided reference signal DF2 are compared with each other. When the oscillation frequency of the first VCO 51a is higher than a desired frequency, the phase error signal ΔDF is generated in the phase comparator 88. The phase error signal ΔDF is added to the charge pump 92 in the control voltage generator 91 and then implemented time integration. A phase error integrated signal SDF provided by the time integration is smoothed by the loop filter 94, and the control voltage Vcontrol is thus provided. The control voltage Vcontrol is sent to the first and second voltage comparators 96 and 98 and then compared with the first and second comparison potentials Vcomp1 and Vcomp2, respectively.
For example, it is assumed that a signal which allows a desired oscillation signal SHF provided within the oscillation frequency band of the third VCO 51c is provided from an external circuit to the first frequency divider 82. In such case, the control voltage Vcontrol provided from the control voltage generator 91 is so high as to exceed the second comparison potential Vcomp2, which is the upper limit potential. Accordingly, the second voltage comparator 98 sends the output signal VC2 to the control circuit 100 so as to provide an instruction to switch to the second VCO 51b having the higher oscillation frequency band.
The control circuit 100 stores the fact that the first VCO 51a has been selected. When the output signal VC2 is sent from the second voltage comparator 98, the control circuit 100 generates the control signal SGC2 to turn on the switch SW2 in order to switch to the higher frequency band. Control signals SGC1, SGC3 and SGC4 are not provided, and the switches SW1, SW3 and SW4 are turned or remain off.
The oscillation signal SHF having the oscillation frequency of the second VCO 51b is processed by the above-described PLL circuit 99, and the control voltage Vcontrol is re-generated. The control voltage Vcontrol is sent into the first and second voltage comparators 96 and 98 and then compared with the first and second comparison potentials Vcomp1 and Vcomp2. However, the control voltage Vcontrol is still higher than the second comparison potential Vcomp2, which is the upper limit potential, and therefore the output signal VC2 providing the instruction to switch to the third VCO 51c having the higher oscillation frequency band is sent from the second voltage comparator 98 to the control circuit 100. The control circuit 100 generates the control signal SGC3 instead of the control signal SGC2 and thereby turns on the switch SW3.
The oscillation signal SHF having the oscillation frequency of the third VCO 51c is similarly processed by the above-described PLL circuit 99. Since the oscillation signal SHF from the third VCO 51c is in the desired frequency band, a phase difference between the divided oscillation signal DF1 and the divided reference signal DF2 is small. Therefore, the small phase error signal ΔDF is generated by the phase comparator 88. Then, the control voltage Vcontrol newly smoothed by the charge pump 92 and loop filter 94 in the control voltage generator 91 is within a voltage range between the first and second comparison potentials Vcomp1 and Vcomp2. Accordingly, the output signals VC1, and VC2 are not generated by the first and second voltage comparators 96 and 98. As a result, the control circuit 100 holds the switch SW3 in an on-state.
Subsequently, in the phase comparator 88, the phases of the divided oscillation signal DF1 and the divided reference signal DF2 are compared with each other, and the phase error signal ΔDF is generated. When no phase difference exist between the divided oscillation signal DF1 and the divided reference signal DF2 as a result of the feedback control by the PLL circuit 99, the lock detector 90 operates to lock the PLL circuit 99. Once the PLL circuit 99 is locked, the control circuit 100 stops the operation of switching the VCOs 51a to 51d thereafter and holds the locked state even if the unlock condition is temporarily detected due to a disturbance. More specifically, as long as the unlock condition is not continuously detected for a predetermined period of time by the lock detector 90, the oscillation signal SHF from the currently selected third VCO 51c is provided from the output node 64.
Next, it is assumed that frequency alteration data are provided to the PLL circuit 99 from the reference signal source 86 to oscillate in a different frequency band. In such case, since the VCOs 51a to 51d having a suitable frequency band are not selected, the phases of a divided oscillation signal DF1 and the divided reference signal DF2 are compared with each other by the phase comparator 88, and the phase error signal ΔDF is detected by the lock detector 90. Since the phase error signal ΔDF is not temporarily detected due to a disturbance, the phase error signal ΔDF is continuously detected over the predetermined period of time. In such case, the PLL circuit 99 is unlocked by the lock detector 90. The control circuit 100 is reset similarly when turning on power, and a control signal SGC1, which is generated in the initial condition, is provided. The control signal SGC1 turns on the switch SW1 to again select the first VCO 51a and controls the other switches SW2 to SW4 to be off. In such way, another search for a suitable VCO having a desired frequency band is performed again.
Note that, when the frequency alteration data is sent from the reference signal source 86 to the PLL circuit 99 to oscillate in a different frequency band, it is possible to achieve an operation similar to the foregoing with a circuitry which resets the control circuit 100 to the initial condition by using a frequency alteration signal of the frequency alteration data.
In the frequency synthesizer according to the second embodiment of the present invention, a plurality of VCOs having different frequency bands can be used for switching the VCOs. Therefore, it is possible to provide a frequency synthesizer which has a small phase noise and a wide variable frequency range.
As shown in
In the second embodiment, as shown in
The VCO 51 includes a resonator 70c connected to an output of a control voltage generator 91; and a negative resistance circuit 60 having an input connected to the resonator 70c, and an output connected between an input of a first frequency divider 82 and an output node 64. In the resonator 70c, a phase adjuster 54 is connected in series to a reactance controller 52 to which the control voltage Vcontrol is sent, and is connected to a plurality of switches SW1 to SW4 connected in parallel to one another. The switches SW1 to SW4 are connected to first to fourth FBARs 56a to 56d, respectively, and output ends of the first to fourth FBARs 56a to 56d are connected to the input of the negative resistance circuit 60. Outputs of the control circuit 100 generating the control signals SGC1 to SGC4 are respectively connected to the switches SW1 to SW4 for the first to fourth FBARs 56a to 56d.
Using FBARs having different film thicknesses, the first to fourth FBARs 56a to 56d are designed such that the respective oscillation frequencies are variable in frequency bands different from one another. As shown in
Moreover, the first to fourth FBARs 56a to 56d are switched in order from the first FBAR 56a to the fourth FBAR 56d, or reversely in order from the fourth FBAR 56d to the first FBAR 56a, using the switches SW1 to SW4 which are switched by the control signals SGC1 to SGC4 from the control circuit 100. Thus, it is possible for the frequency synthesizer to operate in the wide oscillation frequency band from f1Min to f4Max.
In the above description, FBARs having different film thicknesses are used as the first to fourth FBARs 56a to 56d. However, similar effects may be provided by using FBARs having different electrode areas.
As described above, according to the first modification of the second embodiment, since the single VCO 51 is used, it is possible to reduce the size and cost of resonator circuitry. In addition, low power consumption operation can be achieved. Moreover, the VCO 51 may be operated by switching the first to fourth FBARs 56a to 56d having different resonance frequencies by the control circuit 100 sending the control signals SGC1 to SGC4 to the switches SW1 to SW4. Thus, it is possible to provide a frequency synthesizer which has a small phase noise and a wide frequency tunability.
As shown in
The second modification of the second embodiment of the present invention is different from the first modification of the second embodiment in that a switch SW5 for switching the control voltage Vcontrol, connected to an input of the VCO 51 in the PLL circuit 99b, is used. The switch SW5 switches between an output of a control voltage generator 91 and a standard potential VSTD of the voltage comparator 102 by a control signal SGC5 which is provided from the control circuit 100a based on the output signals VCH and VCL from the voltage comparator 102. The other configurations are similar to the first modification of the second embodiment. Therefore, redundant descriptions will be omitted.
In an initial condition, the switch SW5 connected to the input of the VCO 51, is connected to the standard potential VSTD. The standard potential VSTD for the voltage comparator 102 is set to the upper limit of the control voltage Vcontrol for the reactance controller 52 in the resonator 70c. The voltage comparator 102 compares the control voltage Vcontrol with the standard potential VSTD. The voltage comparator 102 sends the output signal VCH to the control circuit 100a when the control voltage Vcontrol is higher than the standard potential VSTD and sends the output signal VCL when the control voltage Vcontrol is lower than the standard potential VSTD.
The control circuit 100a sends any one of the control signals SGC1 to SGC4 to the switches SW1 to SW4 for switching the first to fourth FBARs 56a to 56d in the resonator 70c depending on the output signal VCH or VCL from the voltage comparator 102, in accordance with a predetermined algorithm. Moreover, when the voltage comparator 102 sends the output signal VCL, the control circuit 100a switches the switch SW5 from the standard potential VSTD of the initial condition, to the output of the control voltage generator 91. Therefore, when the oscillation signal SHF from the VCO 51 is set in a desired frequency band, a feedback loop of the PLL circuit 99b is established. The feedback control by the PLL circuit 99b eliminates a phase difference between a divided oscillation signal DF1 and a divided reference signal DF2. Accordingly, the PLL circuit 99b is locked.
Next, a description will be given of the operation of the frequency synthesizer according to the second modification of the second embodiment. The control circuit 100a in the frequency synthesizer uses the algorithm shown in
When turning on power of the frequency synthesizer, the control circuit 10a is reset, and a control signal SGC2 to select the second FBAR 56b as an initial value is generated to turn on only the switch SW2. The switch SW5 is connected to the standard potential VSTD, and the standard potential VSTD is provided to the reactance controller 52 of the resonator 70c in the VCO 51 shown in
In the phase comparator 88, a phase error signal ΔDF is generated. The phase error signal ΔDF is added to the charge pump 92 in the control voltage generator 91 to implement time integration. A phase error integrated signal SDF provided by the time integration is smoothed by the loop filter 94, and thus the control voltage Vcontrol is generated. Since the oscillation frequency using the second FBAR 56b is lower than the desired frequency, the control voltage Vcontrol is higher than the standard potential VSTD for the voltage comparator 102. Accordingly, the output signal VCH is sent from the voltage comparator 102 to the control circuit 100a.
In accordance with the algorithm shown in
Since the oscillation frequency of the oscillation signal SHF generated by using the third FBAR 56c is lower than the desired frequency, the generated control voltage Vcontrol is higher than the standard potential VSTD. Accordingly, the output signal VCH is sent from the voltage comparator 102 to the control circuit 100a. In accordance with the algorithm shown in
The oscillation frequency of the oscillation signal SHF generated by using the fourth FBAR 56d is close to the desired frequency. Then, the generated control voltage Vcontrol is lower than the standard potential VSTD. Accordingly, the output signal VCL is sent from the voltage comparator 102 to the control circuit 100a. Therefore, the control circuit 100a holds the switch SW4 in an on-state. At the same time, the control circuit 100a turns the switch SW5 from the connection to the standard potential VSTD to the connection to the output of the control voltage generator 91. As a result, the control voltage Vcontrol provided from the loop filter 94 is applied to the resonator 70c in the VCO 51, and thus the feedback loop of the PLL circuit 99b is established. The feedback control by the PLL circuit 99b eliminates a phase difference between the divided oscillation signal DF1 and the divided reference signal DF2. Accordingly, the PLL circuit 99b is locked. Thus, the search for the FBAR having a frequency band including a frequency of the reference signal SREF from the reference signal source 86 is implemented following a path indicated by the dashed line in
As described above, according to the second modification of the second embodiment, since the single VCO 51 is used, it is possible to reduce the size and cost of a resonator circuit. In addition, low power consumption operation can be achieved. Moreover, since the single voltage comparator 102 is used to monitor the control voltage Vcontrol so as to compare with the standard potential VSTD, it is possible to simplify the circuitry. Furthermore, the VCO 51 may be operated by switching the first to fourth FBARs 56a to 56d having different resonance frequencies by the control circuit 100 sending the control signals SGC1 to SGC4 to the switches SW1 to SW4 for switching the FBARs. Thus, it is possible to provide a frequency synthesizer which has a small phase noise and a wide frequency tunability.
As shown in
The third modification of the second embodiment is different from the second modification of the second embodiment in that the control circuit 100b sends any one of the control signals SGC1 to SGC4 to the switches SW1 to SW4 for switching the first to fourth FBARs 56a to 56d provided in the VCO 51, based on an up signal DSUP or a down signal DSDOWN according to a phase difference between a divided oscillation signal DF1 and a divided reference signal DF2 from the phase comparator 88a in the PLL circuit 99c. The other configurations are similar to the second modification of the second embodiment. Therefore, redundant descriptions will be omitted.
The operation of the phase comparator 88a will be described using a timing chart shown in
In addition, when the control circuit 100b switches the first to fourth FBARs 56a to 56d by generating any one of the control signals SGC1 to SGC4, the reset signal generator 104 generates the reset signal DSRST so as to simultaneously reset the first and second frequency dividers 82 and 84. Furthermore, the switch SW5 connects an input of the resonator 70c in the VCO 51 with any one of the standard potential VSTD and the control voltage Vcontrol which is the output of the control voltage generator 91, based on the control voltage control signal SGC5 from the control circuit 100b. Note that the standard potential VSTD is set to the upper limit of the control voltage Vcontrol.
Next, a description will be given of the operation of the frequency synthesizer according to the third modification of the second embodiment. The control circuit 100b in the frequency synthesizer uses the algorithm shown in
In the third modification of the second embodiment as well, searching is started with the second FBAR 56b having an intermediate band. When turning on power, the PLL circuit 99c is forced to reset to an initial condition by the control circuit 100b. The control signal SGC2 to select the second FBAR 56b as an initial value is generated to turn on only the switch SW2. In the initial condition, the switch SW5 is connected to the standard potential VSTD. Thus, the standard potential VSTD is provided to the reactance controller 52 of the resonator 70c in the VCO 51. Accordingly, the loop of the PLL circuit 99c is opened in the initial condition. In addition, the standard potential VSTD is set beforehand to the upper limit of the control voltage Vcontrol.
The VCO 51 starts oscillation at a frequency determined by the resonance characteristics of the second FBAR 56b depending on the standard potential VSTD. The first frequency divider 82 divides the oscillation signal SHF of the oscillation frequency to generate a divided oscillation signal DF1. The divided oscillation signal DF1 is sent to the phase comparator 88a. The second frequency divider 84 divides the reference signal SREF to generate a divided reference signal DF2. The divided reference signal DF2 is also added to the phase comparator 88a. In the phase comparator 88a, the phases of the divided oscillation signal DF1 and the divided reference signal DF2 are compared.
The control circuit 100b sends the reset command signal SGRST to the reset signal generator 104. The reset signal generator 104 sends the reset signal DSRST to the first and second frequency dividers 82 and 84. When the reset signal DSRST is received, the first and second frequency dividers 82 and 84 simultaneously start dividing. Since the oscillation frequency of the VCO 51 using the second FBAR 56b is lower than the desired frequency, the falling edge of the divided oscillation signal DF1 provided to the phase comparator 88a is delayed with respect to the falling edge of the divided reference signal DF2. Accordingly, the phase delay of the divided oscillation signal DF1 is detected by the phase comparator 88a. Thus, the generated up signal DSUP is provided to the control circuit 100b.
When the up signal DSUP is provided to the control circuit 100b, the control circuit 100b, in accordance with the algorithm shown in
The oscillation signal SHF provided by the VCO 51 using the third FBAR 56c is added to the first frequency divider 82, and divided into the divided oscillation signal DF1. The divided oscillation signal DF1 is provided to the phase comparator 88a. However, since the third FBAR 56c is selected, oscillation at the desired frequency cannot be provided. Therefore, again, a phase delay of the divided oscillation signal DF1 is detected by the phase comparator 88a. Thus, the up signal DSUP is provided to the control circuit 100b.
When the up signal DSUP is provided to the control circuit 100b, in accordance with the algorithm shown in
The oscillation signal SHF provided by the VCO 51 using the fourth FBAR 56d is added to the first frequency divider 82, and divided into the divided oscillation signal DF1. The divided oscillation signal DF1 is provided to the phase comparator 88a. Since the frequency of the divided oscillation signal DF1 provided by the first frequency divider 82 is higher than that of the divided reference signal DF2, the falling edge of the divided oscillation signal DF1 is advanced with respect to the falling edge of the divided reference signal DF2. Accordingly, the phase advance of the divided oscillation signal DF1 is detected by the phase comparator 88a. Thus, the generated down signal DSDOWN is provided to the control circuit 10b.
As a result, the control signal SGC4 from the control circuit 100b holds the switch SW4 in the on-state. Moreover, at the same time, the control signal SGC5 is sent from the control circuit 100b to turn the switch SW5 from the standard potential VSTD to the output of the control voltage generator 91. Thus, the feedback loop of the PLL circuit 99c is established.
With closing of the PLL circuit 99c, the up signal DSUP or down signal DSDOWN sent from the phase comparator 88a is detected in the control circuit 100b. The reset command signal SGRST is sent from the control circuit 100b to the reset signal generator 104. When the reset signal DSRST are sent from the reset signal generator 104 to the first and second frequency dividers 82 and 84, the first and second frequency dividers 82 and 84 simultaneously start dividing. Therefore, one of the falling edges of the divided oscillation signal DF1 and the divided reference signal DF2 to be provided to the phase comparator 88a, which has a lower frequency, is delayed with respect to the other. In the pull-in processes thereafter, since the operation start times of the first and second frequency dividers 82 and 84 are always synchronized, the phase comparator 88a will compare phases and frequencies at the same time. Therefore, when the frequencies of the outputs of the first and second frequency dividers 82 and 84 are the same, the phases thereof are always the same as well.
Fine adjustment of the oscillation frequency of the VCO 51 is implemented with the feedback control by the PLL circuit 99c. When no phase difference is detected between the divided oscillation signal DF1 and the divided reference signal DF2 in the end as a result of the feedback control, the lock detector 90 operates to lock the phase of the PLL circuit 99c. At the same time, the control circuit 100b stops providing the reset command signal SGRST. Thus, the output frequency of the VCO 51 is stabilized.
In addition, once the PLL circuit 99c is locked, the operation of switching the FBARs is stopped. Even when an unlocking condition is temporarily detected due to a disturbance, the lock condition is held.
As described above, according to the third modification of the second embodiment, since a single VCO 51 is used, it is possible to reduce the size and cost of a resonator circuit. In addition, low power consumption operation can be achieved. Moreover, instead of the control voltage Vcontrol generated by the loop filter 94 in the control voltage generator 91, the up and down signals DSUP and DSDOWN generated by the phase comparator 88a, which is provided in the preceding stage of the control voltage generator 91, are used to search for an FBAR having a suitable frequency band. Therefore, it is possible to reduce the time required for searching for an FBAR. Furthermore, the VCO 51 can be operated by switching the first to fourth FBARs 56a to 56d having different resonance frequencies by the control circuit 100b generating the control signals SGC1 to SGC4 of the switches SW1 to SW4 for switching the FBARs. Thus, it is possible to provide a frequency synthesizer which has a small noise and a wide frequency tunability.
As shown in
The fourth modification of the second embodiment is different from the third modification of the second embodiment in that any one of the control signals SGC1 to SGC4 for the switches SW1 to SW4 for switching the first to fourth FBARs 56a to 56d provided in the VCO 51 is generated based on the phase discrimination signal DSPH generated by the phase discriminator 106. The other configurations are similar to the third modification of the second embodiment. Therefore, redundant descriptions will be omitted.
The divided oscillation signal DF1 and the divided reference signal DF2 sent from the first and second frequency dividers 82 and 84 respectively, are not only provided to the phase comparator 88 but also provided to the phase discriminator 106. The phase discriminator 106 compares the phases of the divided oscillation signal DF1 and the divided reference signal DF2 and thereby determines whether the phase of the divided oscillation signal DF1 delays or advances with respect to that of the divided reference signal DF2. Then, the phase discriminator 106 provides the result of the determination as the phase discrimination signal DSPH to the control circuit 100c. As for the comparison of the phases of the divided oscillation signal DF1 and the divided reference signal DF2, in a similar way to that shown in
In the fourth modification of the second embodiment as well, searching for an FBAR having a suitable frequency band is started with the second FBAR 56b having an intermediate frequency band. When turning on power, the PLL circuit 99d is forced to reset to an initial condition by the control circuit 100c. The control signal SGC2 to select the second FBAR 56b as an initial value is generated to turn on only the switch SW2. In the initial condition, the switch SW5 is connected to the standard potential VSTD. Thus, the standard potential VSTD is provided to the reactance controller 52 of the resonator 70c in the VCO 51. Accordingly, the loop of the PLL circuit 99d is opened in the initial condition. In addition, the standard potential VSTD is set beforehand to the upper limit of the control voltage Vcontrol.
When the reset command signal SGRST is sent from the control circuit 100c to the reset signal generator 104, the reset signal DSRST is sent from the reset signal generator 104 to the first and second frequency dividers 82 and 84. Due to the reset signal DSSRT, the oscillation signal SHF and the reference signal SREF are simultaneously divided by the first and second frequency dividers 82 and 84, respectively. As a result, the divided oscillation signal DF1 and the divided reference signal DF2 are provided to the phase comparator 88 and the phase discriminator 106. When it is determined by the phase discriminator 106 that the phase of the divided oscillation signal DF1 is delayed with respect to that of the divided reference signal DF2, the phase discrimination signal DSPH indicating a phase delay is provided to the control circuit 100c. In the control circuit 100c, based on the phase discrimination signal DSPH, the control signal SGC3 to turn on the switch SW3 is generated to select the third FBAR 56c in place of the currently selected second FBAR 56b. The switch SW5 is held in connection with the standard potential VSTD. Thus, the loop of the PLL circuit 99c is held open. Further, the reset command signal SGRST is sent from the control circuit 100c to the reset signal generator 104, and the above-described search for the FBAR is continued.
When the fourth FBAR 56d is selected and it is determined by the phase discriminator 106 that the phase of the divided oscillation signal DF1 is advanced with respect to that of a divided reference signal DF2, the phase discrimination signal DSPH indicating a phase delay is provided to the control circuit 100c. As a result, the control signal SGC4 from the control circuit 100c holds the switch SW4 in the on-state. At the same time, the control signal SGC5 is sent from the control circuit 100c and turns the switch SW5 from the standard potential VSTD to the output of the control voltage generator 91. Thus, the feedback loop of the PLL circuit 99c is established. The feedback control by the PLL circuit 99c eliminates a phase difference between the divided oscillation signal DF1 and the divided reference signal DF2. Thus, the PLL circuit 99c is locked.
As described above, according to the fourth modification of the second embodiment, since the single VCO 51 is used, it is possible to reduce the size and cost of a resonator circuit. In addition, low power consumption operation can be achieved. Moreover, since the phases of the divided oscillation signal DF1 and the divided reference signal DF2 are compared by the phase discriminator 106 in order to search for an FBAR having a suitable frequency band, it is possible to reduce the time required for searching for an FBAR. Furthermore, the VCO 51 can be operated by switching the first to fourth FBARs 56a to 56d having different resonance frequencies by the control circuit 100c generating the control signals SGC1 to SGC4 of the switches SW1 to SW4 for switching the FBARs. Thus, it is possible to provide a frequency synthesizer which has a small noise and a wide frequency tunability.
As shown in
The first and second counters 107 and 108 are connected to outputs of the first and second frequency dividers 82 and 84, respectively. The output of the reset signal generator 104a connected to the control circuit 100d, is connected to the first and second frequency dividers 82 and 84 and to the first and second counters 107 and 108. An output of the time difference detector 110, to which the outputs of the first and second counters 107 and 108 and of the reference signal source 86 are connected, is connected to the control circuit 100d. The control circuit 100d is connected to the switches SW1 to SW4 for switching the FBARs in the VCO 51 and to the switch SW5.
In the fifth modification of the second embodiment, the first and second counters 107 and 108 count a predetermined number of the pulses in the divided oscillation signal DF1 and the divided reference signals DF2, which are sent from the first and second frequency dividers 82 and 84, respectively. Thereafter, the first and second counters 107 and 108 provided the first and second counting end signals SCE1 and SCE2, respectively, to the time difference detector 110. The time difference detector 110 calculates a number of reference signals SREF within a time difference between the first and second counting end signals SCE1 and SCE2 and provides the calculated number, as the time difference signal SCTD, to the control circuit 100d. Based on the time difference signal SCTD, the control circuit 100d generates any one of the control signals SGC1 to SGC4 of the switches SW1 to SW4 for switching the first to fourth FBARs 56a to 56d provided in the VCO 51. The fifth modification of the second embodiment is different from the third modification of the second embodiment in the above-discussed points. The other configurations of the fifth modifications of the second embodiment are similar to the third modifications of the second embodiment. Therefore, redundant descriptions will be omitted.
In the fifth modification of the second embodiment as well, searching for an FBAR having a suitable frequency band is started with the second FBAR 56b having an intermediate frequency band. When turning on power, the PLL circuit 99e is forced to reset to an initial condition by the control circuit 100d. The control signal SGC2 to select the second FBAR 56b as an initial value is sent from the control circuit 100d to turn on only the switch SW2. In the initial condition, the switch SW5 is connected to the standard potential VSTD. Thus, the standard potential VSTD is provided to the reactance controller 52 of the resonator 70c in the VCO 51. Accordingly, the loop of the PLL circuit 99e is opened in the initial condition. In the fifth modification of the second embodiment, the standard potential VSTD is set beforehand to an intermediate potential between the upper limit and lower limit of the control voltage Vcontrol.
The reset command signal SGRST is sent to the reset signal generator 104a from the control circuit 10d. The reset signal generator 104a provides the reset signal DSRST to the first and second frequency dividers 82 and 84, and the count reset signal SCRST to the first and second counters 107 and 108. The first and second frequency dividers 82 and 84 simultaneously start dividing so as to generate the divided oscillation signals DF1 and the divided reference signals DF2, respectively. The first and second counters 107 and 108 simultaneously start counting the divided oscillation signals DF1 and the divided reference signals DF2 sent from the first and second frequency dividers 82 and 84, respectively.
When the first and second counters 107 and 108 finish counting the predetermined number of pulses, the first and second counters 107 and 108 send the first and second counting end signal SCE1 and SCE2, respectively, to the time difference detector 110. When the time difference detector 110 detects the earlier one of the first and second counting end signals SCE1 and SCE2, the time difference detector 110 starts counting reference signals SREF. The counting is continued until the later one of the first and second counting end signals SCE1 and SCE2 is detected. When the first counting end signal SCE1 is earlier, a positive sign is provided to a resulting value. When the second counting end signal SCE2 is earlier, a negative sign is provided to a resulting value. The counting result is sent to the control circuit 100d as the time difference signal SCTD.
In the control circuit 10d, a frequency difference having the positive or negative sign is calculated from the time difference signal SCTD. Then, it is determined whether or not an FBAR in the VCO 51 needs switching. Moreover, the control circuit 100d stores information of the currently selected second FBAR 56b. When an FBAR needs switching, the FBAR having a suitable frequency band is selected from among the first to fourth FBAR 56a to 56d, based on the calculated frequency difference. For example, when the time difference signal SCTD has a positive sign, the FBAR 56b is switched to an FBAR having a lower frequency band. When the time difference signal SCTD has a negative sign, the FBAR 56b is switched to an FBAR having a higher frequency band.
In the fifth modification of the second embodiment, for example, it is assumed that it is determined that an FBAR having a suitable frequency band is the fourth FBAR 56d which has a two-level higher frequency band than the second FBAR 56b. In such case, the control signal SGC4 is sent from the control circuit 100d so as to turn on the switch SW4. Accordingly, in the resonator 70c, the fourth FBAR 56d having the suitable oscillation frequency band is selected instead of the currently selected second FBAR 56b. In addition, the switch SW5 is held in connection with the standard potential VSTD.
Subsequently, the reset command signal SGRST is sent again to the reset signal generator 104a from the control circuit 10d. Thus, the first and second counters 107 and 108 simultaneously start counting again. When the first and second counters 107 and 108 finish counting the predetermined number of respective pulses the first and second counters 107 and 108 provide the first and second counting end signals SCE1 and SCE2, respectively, to the time difference detector 110. The time difference detector 110 calculates the number of reference signals SREF within a time difference between the first and second counting end signals SCE1 and SCE2. The calculating result is sent to the control circuit 100d as the time difference signal SCTD.
The control circuit 100d calculates a frequency difference from the time difference signal SCTD. Since the fourth FBAR 56d having a suitable frequency band has already been selected, a magnitude of the time difference signal SCTD is in a predetermined tolerance level. Accordingly, it is determined that the FBAR does not need switching. As a result, the control signal SGC5 is sent from the control circuit 100d to turn the switch SW5 from the standard potential VSTD to the output of the loop filter 94 in the control voltage generator 91. Thus, the feedback loop of the PLL circuit 99e is closed.
The control circuit 100d continues monitoring the oscillation frequency of the VCO 51 for a period of time after the feedback loop of the PLL circuit 99e is closed until the phase lock is detected by the lock detector 90, using the first and second counters 107 and 108 and the time difference detector 110. In the meantime, the control circuit 100d continues monitoring the oscillation frequency by using time difference signals SCTD sent from the time difference detector 110. Additionally, the control circuit 100d sends the reset command signal SGRST to the reset signal generator 104a when the time difference signal SCTD is greater than a reference value for the phase lock of the feedback loop of the PLL circuit 99e. The reset signal generator 104a provides the reset signal DSRST to the first and second frequency dividers 82 and 84 respectively, and the count reset signal SCRST to the first and second counters 107 and 108 respectively. For every reception of the reset signal DSRST and the count reset signal SCRST, the first and second frequency dividers 82 and 84 simultaneously start dividing, and the first and second counters 107 and 108 simultaneously start counting. In such way, the dividing start time for the first and second frequency dividers 82 and 84 are always synchronized in the pull-in process. Further, when the divided oscillation signal DF1 and the divided reference signal DF2 respectively sent from the first and second frequency dividers 82 and 84 is the same, the phases of these signals is always the same as well. Thus, when the phase lock is finally detected by the lock detector 90, the control circuit 100d stops providing the reset command signal SGRST to the reset signal generator 104a.
As described above, according to the fifth modification of the second embodiment, since the single VCO 51 is used, it is possible to reduce the size and cost of a resonator circuit. In addition, low power consumption operation can be achieved. Moreover, in order to search for an FBAR having a suitable frequency band, the suitable frequency band is determined based on the frequency difference between the divided oscillation signal DF1 and the divided reference signal DF2, using the first and second counters 107 and 108 and the time difference detector 110. Accordingly, it is possible to reduce the time required for searching for an FBAR. Furthermore, the VCO 51 can be operate by switching the first to fourth FBARs 56a to 56d having different resonance frequencies by the control circuit 100d generating the control signals SGC1 to SGC4 of the switches SW1 to SW4 for switching the FBAR. Thus, it is possible to provide a frequency synthesizer which has a small noise and a wide frequency tunability.
As shown in
The counter 112 is connected to an output node 64 of the VCO 51 and an output of the second frequency divider 84. An output of the counter 112 is connected to the control circuit 100e. Moreover, the control circuit 100e is connected to the reset signal generator 104a, and an output of the reset signal generator 104a is connected to the first and second frequency dividers 82 and 84. The control circuit 100e is also connected to the switches SW1 to SW4 for switching first to fourth FBARs 56a to 56d in the VCO 51 and to the switch SW5.
By receiving an input of a divided reference signal DF2 to be used as the count reset signal, the counter 112 counts the number of pulses in the oscillation signal SHF from the VCO 51 until the next divided reference signal DF2 is received. The control circuit 10e calculates a frequency difference between the oscillation signal SHF and a desired frequency, based on the count signal SCCNT sent from the counter 112 and on the count standard value SCSTD. The control circuit 10e determines whether to switch the first to fourth FBARs 56a to 56d depending on the frequency difference calculation based on the count signal SCCNT and the count standard value SCSTD. The standard count value SCSTD is altered based on frequency data provided to the reference signal source 86 so as to respond to a suitable frequency. The control circuit 10e generates any one of control signals SGC1 to SGC4 of the switches SW1 to SW4 for switching the first to fourth FBARs 56a to 56d in the VCO 51, based on the frequency difference calculated using the count signal SCCNT and the standard count value SCSTD. The sixth modification of the second embodiment is different from the fifth modification of the second embodiment in the above-discussed points. The other configurations of the sixth modifications of the second embodiment are similar to the fifth modifications of the second embodiment. Therefore, redundant descriptions will be omitted.
In the sixth modification of the second embodiment, searching for the FBAR having a suitable frequency band is started with the second FBAR 56b having an intermediate band. When turning on power, the PLL circuit 99f is forced to reset to an initial condition by the control circuit 100e. The control signal SGC2 to select the second FBAR 56b as an initial value is sent from the control circuit 100e to turn on only the switch SW2. In the initial condition, the switch SW5 is connected to the standard potential VSTD. Thus, the standard potential VSTD is provided to the reactance controller 52 of the resonator 70c in the VCO 51. Accordingly, the loop of the PLL circuit 99f is opened in the initial condition. In the sixth modification of the second embodiment, the standard potential VSTD is set beforehand to an intermediate potential between the upper and lower limits of the control voltage Vcontrol.
The oscillation signal SHF generated by the VCO 51 using the second FBAR 56b and the divided reference signal DF2 are provided to the counter 112. When the divided reference signal DF2 is received, the count in the counter 12 is reset. The counter 12 counts the number of pulses in the oscillation signal SHF until the next divided reference signal DF2 is received, and sends the count value, as the count signal SCCNT, to the control circuit 100e.
The control circuit 100e calculates a frequency difference by comparing the count signal SCCNT with the count standard value SCSTD and determines whether or not the FBAR in the VCO 51 needs switching. Moreover, the control circuit 100e stores information of the currently selected second FBAR 56b. When the FBAR needs switching, an FBAR having a suitable frequency band is selected based on the calculated frequency difference. For example, when the count signal SCCNT is greater than the standard count value SCSTD, an FBAR having a lower frequency band is selected, instead of the second FBAR 56b. When the count signal SCCNT is smaller than the standard count value SCSTD, an FBAR having a higher frequency band is selected.
In the sixth modification of the second embodiment, for example, it is assumed that it is determined that an FBAR having a suitable frequency band is the fourth FBAR 56d which has a two-level higher frequency band than the second FBAR 56b. In such case, the control signal SGC4 is sent from the control circuit 10e so as to turn on the switch SW4. Accordingly, in the resonator 70c, the fourth FBAR 56d having a suitable oscillation frequency band is selected instead of the currently selected second FBAR 56b. In addition, the switch SW5 is held in connection with the standard potential VSTD.
Subsequently, the reset command signal SGRST is sent to the reset signal generator 104a from the control circuit 10e. The reset signals DSRST are sent to the first and second frequency dividers 82 and 84 from the reset signal generator 104a. Triggered by these signals, the first and second frequency dividers 82 and 84 start dividing again. The oscillation signals SHF generated by oscillation by the VCO 51 using the fourth FBAR 56d and the divided reference signal DF2 are provided to the counter 112. When the divided reference signal DF2 is received, the count in the counter 112 is reset, and the number of pulses in the oscillation signals SHF are counted until the next divided reference signal DF2 is received. The count value is sent to the control circuit 10e as a count signal SCCNT.
The control circuit 10e calculates a frequency difference by comparing the count signal SCCNT and the standard count value SCSTD. Since the fourth FBAR 56d having a suitable frequency band has already been selected, the frequency difference is within a predetermined tolerance level. Accordingly, it is determined that the FBAR does not need switching. As a result, the control signal SGC5 is sent from the control circuit 10e to turn the switch SW5 from the standard potential VSTD to the output of the loop filter 94 in the control voltage generator 91. Thus, the feedback loop of the PLL circuit 99f is closed.
As described above, according to the sixth modification of the second embodiment, since a single VCO 51 is used, it is possible to reduce the size and cost of a resonator circuit. In addition, low power consumption operation can be achieved. Moreover, in order to search for an FBAR having a suitable frequency band, the suitable frequency band is determined by monitoring the oscillation signals SHF using the counter 112. Accordingly, it is possible to reduce the time required for searching for an FBAR. Furthermore, the VCO 51 can be operated by switching the first to fourth FBARs 56a to 56d having different resonance frequencies by the control circuit 10e generating the control signals SGC1 to SGC4 of the switches SW1 to SW4 for switching the FBAR. Thus, it is possible to provide a frequency synthesizer which has a small noise and a wide frequency tunability.
As shown in
The control circuit 100f generates control signals SGC1 to SGC4 to select switches SW1 to SW4 for switching the FBARs in the first and second VCOs 51e and 51f. Moreover, the control circuit 100f provides a control signal SGCC to a switch SWVCO for the first and second VCOs 51e and 51f.
In the seventh modification of the second embodiment, in order to search for a suitable VCO and a suitable FBAR, any one set of control signals SGC1 and SGC2 for the first and second FBARs 56a and 56b respectively, control signals SGC2 and SGC3 for the second and third FBARs 56b and 56c respectively, and control signals SGC3 and SGC4 for the third and fourth FBARs 56c and 56d respectively, are simultaneously generated. As described using
In the seventh modification of the second embodiment, for example, as an initial condition, the control signals SGC1 and SGC2 of the switches SW1 and SW2 are sent from the control circuit 100f to turn on the first and second FBARs 56a and 56b in the first and second resonators 70d and 70e respectively. Then, the first and second VCOs 51e and 51f are oscillated. In addition, the switch SWVCO is connected to the first VCO 51e.
When the oscillation signal SHF generated by the first VCO 51e using the first FBAR 56a is not in a desired oscillation frequency band, the control signal SGCC is sent from the control circuit 10f, and the switch SWVCO is connected to the second VCO 51f. At the same time, the control signal SGC1 of the switch SW1 is turned off, and a control signal SGC3 of the switch SW3 is sent from the control circuit 100f to turn on the third FBAR 56c in the first resonator 70d. As a result, if the oscillation signal SHF generated by the second VCO 51f using the second FBAR 56b is determined to be the desired oscillation frequency band, the first VCO 51e starts oscillation using the third FBAR 56c.
In the seventh modification of the second embodiment, while the oscillation signal SHF generated by one of the VCOs 51e and 51f, which is connected to the PLL circuit 99g by the switch SWVCO, is determined to be a desired oscillation frequency band, the FBARs are switched in the other VCO, and the other VCO oscillates in a steady state by using the newly selected FBAR. Further, when it is determined by the control circuit 100f that the oscillation signal SHF is in the desired oscillation frequency band, the control circuit 100f stops generating the control signals of the FBARs in the VCO which is not connected to the PLL circuit 99g by the Switch SWVCO. Accordingly, once searching for an FBAR is finished, only one of the VCOs 51e and 51f remains in operation. Thus, it is possible to reduce power consumption.
As described above, according to the seventh modification of the second embodiment, since the two VCOs 51e and 51f which are simultaneously operated are switched by the switch SWVCO, it is possible to search for an FBAR having a suitable frequency band in a shorter period of time. Moreover, since only one VCO is used after searching for an FBAR, low power consumption operation can be achieved. Furthermore, the VCOs 51e and 51f can be operated by switching the first to fourth FBARs 56a to 56d having different resonance frequencies by the control circuit 100f generating the control signals SGC1 to SGC4 of the switches SW1 to SW4. Thus, it is possible to provide a frequency synthesizer which has a small phase noise and a wide frequency tunability.
As shown in
The receiving unit 142 includes an RF receiver 126 connected to the antenna 122 via a duplexer 124; a down converter (D/C) 128 connected to the RF receiver 126 and to the frequency synthesizer 120; and an IF receiver 130 connected to the D/C 128. The IF receiver 130 is connected to the baseband processor 140.
The transmitting unit 144 includes an IF transmitter 132 connected to the baseband processor 140; an up converter (U/C) 134 connected to the IF transmitter 132 and to the frequency synthesizer 120; and an RF transmitter 136 connected to the U/C 134. The RF transmitter 136 is connected to the antenna 122 via the duplexer 124.
When the communication apparatus according to the application of the second embodiment of the present invention receives an RF receiving signal for communication, the duplexer 124 for the antenna 122 is switched to a connection with the receiving unit 142. In the RF receiver 126 of the receiving unit 142, the RF receiving signal, which has passed through a desired receiving frequency band by using, such as, a band-pass filter, is amplified by a low noise amplifier. In the D/C 128, the amplified RF receiving signal is converted into an IF receiving signal with an intermediate frequency by using an oscillation signal sent from the frequency synthesizer 120. In the IF receiver 130, the IF receiving signal, converted to a frequency in an intermediate frequency band, is subjected to signal processing, such as waveform shaping. The IF receiving signal processed in the IF receiver 130 is provided to the baseband processor 140. In the baseband processor 140, a demodulated signal is generated which is provided by demodulating the IF receiving signal.
Moreover, when a transmitting signal for communication is provided to the baseband processor 140, the transmitting signal is modulated in the baseband processor 140. The modulated transmitting signal is subjected to signal processing in the IF transmitter 132 of the transmitting unit 144. In the U/C 134, the signal-processed transmitting signal is converted into an RF transmitting signal by using an oscillation signal sent from the frequency synthesizer 120. In the RF transmitter 136, the RF transmitting signal provided by converting the signal-processed transmitting signal, is passed through a desired frequency band by using, such as, a band-pass filter and is also power-amplified by a power amplifier. The power-amplified RF transmitting signal is transmitted from the antenna 122 via the duplexer 124 which has been switched to connect to the transmitting unit 144.
In the application of the second embodiment, a frequency synthesizer including a VCO having FBARs is used, which has a small phase noise and a wide frequency tunability. Accordingly, it is possible to achieve a wireless communication apparatus capable of stability transmitting and receiving high quality bulk information.
The present invention has been described as discussed above. However the descriptions and drawings that constitute a portion of this disclosure should not be perceived as limiting this invention. Various alternative embodiments and operational techniques will become clear to persons skilled in the art from this disclosure.
In the second embodiment, the description has been given using the negative resistance circuit 60 in the VCO. However, as shown in
Moreover, as shown in
Since the CMOS inverter 80 used in the negative resistance circuit 60a or 60b is superior to a bipolar transistor in terms of integration and manufacturing, the CMOS inverter is advantageous in reducing the size and cost of the VCO 51h or 51g. Moreover, development of a high-frequency CMOS analog circuit is advanced, which may facilitate merged installation of a high frequency analog circuit and a digital circuit.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-201199 | Jul 2003 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 4134085 | Driscoll et al. | Jan 1979 | A |
| 5821820 | Snider et al. | Oct 1998 | A |
| 6411171 | Itoh | Jun 2002 | B2 |
| 6710669 | Hasegawa et al. | Mar 2004 | B2 |
| 6724270 | Kozu | Apr 2004 | B2 |
| 6741137 | Sibrai et al. | May 2004 | B1 |
| 6747529 | Abe et al. | Jun 2004 | B2 |
| 6933793 | Patterson et al. | Aug 2005 | B2 |
| 20030160660 | Chang et al. | Aug 2003 | A1 |
| 20040033794 | Korden et al. | Feb 2004 | A1 |
| 20040198288 | Sadowski | Oct 2004 | A1 |
| 20040227578 | Hamalainen | Nov 2004 | A1 |
| 20050059375 | Abe et al. | Mar 2005 | A1 |
| Number | Date | Country |
|---|---|---|
| 06-120416 | Apr 1994 | JP |
| 6-268443 | Sep 1994 | JP |
| 2001-60870 | Mar 2001 | JP |
| 2001-237699 | Aug 2001 | JP |
| 2002-111492 | Apr 2002 | JP |
| 2002-135055 | May 2002 | JP |
| 2002-185318 | Jun 2002 | JP |
| 2002-261607 | Sep 2002 | JP |
| 2002-344242 | Nov 2002 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20050059375 A1 | Mar 2005 | US |
