Voltage regulator for a charge pump circuit

Abstract

A circuit for regulating an output voltage of a charge pump includes a regulator connected to an output of the charge pump. The regulator includes a voltage divider for dividing the output voltage. A filter has a first input for receiving the divided output voltage, a second input for receiving a control signal, and an output for providing a filtered divided output voltage. A comparator has a first input for receiving the divided output voltage, a second input for receiving a reference voltage, a third input for receiving the filtered divided output voltage, and an output for providing a digital signal based upon a comparison of the divided output signal, the reference voltage and the filtered divided output voltage. A logic control circuit has a first input for receiving a clock signal, a second input for receiving the digital signal from the comparator, and an output for providing a timing signal. A phase generator circuit has an input for receiving the timing signal from the logic control circuit for generating control phases for the charge pump.

Description

FIELD OF THE INVENTION

[0001] The present invention relates in general to integrated digital circuits, and more particularly, to a voltage regulator for a charge pump generating a high voltage (HV) starting from the supply voltage of the integrated circuit.

BACKGROUND OF THE INVENTION

[0002] In EEPROM memory devices it is necessary to keep the high voltage, generated by the charge pump for programming and erasing operations (12-15 V), as constant as possible independently of the required driving capability, which is on the order of tens of μA. It is important that a certain and stable output voltage Vout be produced to ensure that it will not surpass the limit imposed by the dielectric strength of oxides of transistor structures, as well as of capacitors, to prevent the risk of permanently damaging them.

[0003] The basic diagram of FIG. 1 illustrates a commonly implemented regulator. A desired Vreg (regulation voltage) is generated inside the integrated device, based on a known and very stable voltage reference (BandGap circuit), and is input to a comparator that compares it with the output voltage Vout of the charge pump.

[0004] When Vout>Vreg, the regulator sends a logic signal VON to a control circuit that stops the application of clock pulses to the phase generator. As a consequence, the charge pump starts to discharge, and as soon as Vout<Vreg, the regulator re-enables the driving action of the clock on the phase generator.

[0005] With this feedback, a dynamic equilibrium at the steady state condition Vout=Vreg is eventually reached. In a loadless condition, the charge pump is practically turned off, with the evident advantage (especially for minimizing power consumption) of not wasting power. When a load absorbs current, the regulator enables clock pulses to drive the charge pump at a frequency f0 sufficient for precisely compensating the drop of Vout because of the delivering of an electrical charge.

[0006] The current-voltage characteristic of an N stage pump of capacitance C, supplied at the supply voltage Vdd and regulated with a frequency f0≦fmax is shown in FIG. 2. The charge pump generates a constant output voltage Vout=Vreg for any load current, up to the current I0,max compatible with that voltage.

[0007] When the load absorbs a certain current I0, the regulator adjusts the frequency of the clock pulses that reach the phase generator in the neighborhood of a frequency f0 smaller than fmax, making the pump work at the operating point (Vout=Vreg, Iout=I0). In practice, it is as if the slope of the load line had been modified to determine the appropriate output resistance Rout.

[0008] The ideal characteristic of FIG. 2 satisfies the following equation: 1$I_{\mathrm{out}}=\frac{\mathrm{fC}}{N}\left(\left(N+1\right)V_{\mathrm{dd}}-V_{\mathrm{out}}\right)$

[0009] FIG. 3 shows a commonly used regulator circuit. The circuit uses a resistive voltage divider by which a certain fraction VR of the output voltage Vout is tapped and compared by a comparator with the reference voltage VBG usually produced by a bandgap circuit. The output VON of the comparator is a logic signal that enables or disables the passage of clock pulses from the oscillator to the phase generator. Moreover, a properly dimensioned capacitive network is connected in parallel to the voltage divider for reasons that will be explained in the following paragraph.

[0010] The regulated voltage (in terms of mean value) is equal to: 2$V_{\mathrm{out}}=V_{\mathrm{BG}}\left(1+\frac{R_{\mathrm{UP}}}{R_{\mathrm{DOWN}}}\right)$

[0011] The precision of the regulator is tied essentially to the speed with which the node VR responds to voltage variations of Vout for restoring the condition VR=VBG. If the resistors were ideal, the response would be instantaneous. In reality, the variation of Vout propagates to the input of the comparator only after the voltage on the parasitic (distributed) capacitances associated with the integrated resistors have changed, and this slows down the response of the regulation loop.

[0012] In order to compensate this effect, a capacitor CUP is introduced between the node Vout and the node VR, the size of which is chosen based upon a simulated step response, as depicted in FIG. 4. With only the resistive line, the voltage VR increases quite slowly following a sub-compensated characteristic (curve a). Taking into consideration possible uncontrollable variations of parameters, instead of compensating exactly, it is often preferable to overcompensate, in order to benefit from an enhanced reactivity of the control loop.

[0013] To avoid an undershoot (curve b) that would imply an overshoot of the regulated voltage (because the comparator would consider the interval in which VR<VBG as an absence of regulation, thus letting clock pulses reach the phase generator and thus increasing the HVP level), the value of CUP is increased until the undershoot becomes null (curve c). Finally, for reducing the over-elongation peak that could cause spurious switching of the comparator, a capacitor CDOWN, about four times greater than CUP, is used (curve d).

[0014] This common regulation system is subject to dynamic problems. The more frequently the regulator must intervene (that is, the higher is the current required to be delivered by the charge pump), less readily the voltage VR follows the variations of the output voltage Vout. In other words, the response of the regulation loop becomes slower as the load current increases, and any inaccuracy of regulation in terms of an offset (difference) VR−VBG present at the input of the comparator implies an error on Vout that is equal to the offset itself amplified by the ratio RUP/RDOWN, and it may even be on the order of hundreds of mVs.

[0015] With modern technologies, this problem becomes even more severe. The reduced value of the bandgap voltage (−840 mV versus −1.38 V for older technologies), coupled to a high value of RUP (for reducing current consumption through the voltage divider), renders even more difficult accurate regulation of the voltage Vout, and indeed errors of up to 300-400 mV are not infrequent.

SUMMARY OF THE INVENTION

[0016] In view of the foregoing background, the purpose of the present invention is to overcome the above described difficulties.

[0017] The objective has been fully achieved by adopting an innovative technique that includes comparing the reference bandgap voltage not only with the instantaneous value of VR, as it is normally done, but also with a filtered replica thereof obtained by the use of an RC low-pass filter. In this way, even the average value of VR, hereinafter called VRfilter, is accounted for compensating an eventual offset that may be present and that, as we have seen in the known circuits, causes a magnified error on the regulated voltage (normally the magnifying ratio RUP/RDOWNis about 12).

[0018] An objective is thus to provide a regulator for a HV charge pump, capable of self adapting itself to the varying level of the load current, compensating the variation of the regulating effect that normally occurs between extreme operating conditions (that is, near a null load and the maximum load).

[0019] According to the present invention, a regulator of the output voltage of a charge pump operates through the whole range of variation of the current absorbed by the load of the charge pump The regulator comprises a voltage divider for the output voltage of the charge pump for tapping a certain fraction of the output voltage, and a comparator for comparing the tapped voltage fraction with a constant reference voltage applied to respective inputs of the comparator and outputting a resultant digital signal. A logic control circuit is input with a main clock signal and outputs a timing signal, the frequency of which is determined by the state of the digital signal at every pulse of the main clock signal. A circuit generates control phases of the charge pump as a function of the timing signal.

[0020] The regulator is characterized in that it further comprises a low-pass filter for the output voltage fraction, the time constant of which is automatically switched at least between two pre-established values as a function of a certain control signal generated by an integrating circuit to an input of which an inverted replica of the digital signal generated by the comparator is applied. The filtered voltage fraction is applied to a third offset input of the comparator.

[0021] According to an embodiment, the comparator has a first high gain branch, from which the output digital signal is derived, composed by a single NMOS transistor driven by the output of the low-pass filter and electrically connected in parallel to a plurality of NMOS transistors identical to the single NMOS transistor but driven in common by the fraction of the output voltage.

[0022] The other branch of the comparator is identical to the first branch but the single NMOS transistor and the plurality of NMOS transistors are all driven in common by the constant reference voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG. 1 is a commonly known block diagram of the regulating loop of a charge pump according to the prior art.

[0024] FIG. 2 illustrates the characteristics of the regulated charge pump of FIG. 1.

[0025] FIG. 3 shows a commonly used circuit for implementing the regulator block according to the prior art.

[0026] FIG. 4 illustrates the step response of the regulation circuit of FIG. 3.

[0027] FIG. 5 shows a circuit embodiment of the comparator used in the regulator of the present invention.

[0028] FIG. 6 shows a circuit embodiment of an RC low-pass filter used in the regulator of the present invention.

[0029] FIG. 7 illustrates the switchable pass band of the RC filter of FIG. 6.

[0030] FIG. 8 shows a circuit embodiment of the integrator used in the regulator of the present invention.

[0031] FIG. 9 shows frequency response curves according to the present invention.

[0032] FIG. 10 is a block diagram of the regulator for a charge pump according to the present invention.

[0033] FIG. 11 shows comparative results of a simulation with variable current according to the present invention.

[0034] FIGS. 12 a and 12b illustrate the response to a step current variation of a known regulator and of the regulator of the present invention.

[0035] FIGS. 13 a and 13b show comparative responses to a current step according to the present invention.

[0036] FIG. 14 a and 14b show comparative responses to the current step under different conditions according to the present invention.

[0037] FIG. 15 shows the frequency variation of the control signal slow according to the present invention.

[0038] FIGS. 16 a and 16b are diagrams of VR and VRfilter with regulation at 40 μA and at a zero load according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] According to an embodiment of the comparator shown in FIG. 5, the comparator has a first high gain branch for generating the output voltage VON composed of a single NMOS transistor, driven by VRfilter, and connected in parallel to three NMOS transistors. The three NMOS transistors are connected together in series, driven by VR and are identical to the single NMOS transistor. The other branch is identically structured but all transistors are driven by the bandgap voltage VBG.

[0040] The functioning principle is as follows. Assume that the mean value of VR is greater than VBG. The transistor M1 will be more conducting than M2, thus contributing in letting the comparator output switch low (VON low=>regulated output, the passage of clock pulses to the phase generator steps), thus introducing a compensative offset that tends to nullify the difference VRfilter−VBG. This happens independently from the comparison between VR and VBG that is performed by the two internal branches of the comparator formed by an identical series connection of three transistors. Similarly, when VRfilter<VBG, the transistor M1 will be less conducting than M2 unbalancing the comparator toward the opposite condition (VON high=>non regulated output, the clock pulses are fed to the phase generator of the charge pump).

[0041] Preferably, all the NMOS transistors of the comparator are identical in size for simplifying the layout and, in order to attribute a different weight to the effect of voltages VR and VRfilter, three transistors driven by VR (equivalent to a transistor three times longer than M1, thus with an overall gain reduced to a third compared to the gain of M1) are used.

[0042] An embodiment of the adaptive RC filter is shown in FIG. 6. The filter resistance is formed by a first integrated resistor R1, and by a second integrated resistor R2 that may be short-circuited by a CMOS switch controlled by the phases slow and {overscore (slow)} for reducing the time constant of the filter, and thus increasing its pass band. This increments the speed with which the regulator reacts to fast variations of the regulated output voltage. In fact, the value of the current absorbed by the load of the charge pump may change with a frequency that depends on the currently required operations, and cannot be known in advance.

[0043] FIG. 7 shows the frequency response of the filter of FIG. 6 (Bode diagram of the module) in the two possible configurations, corresponding to a (3 dB) cut-off frequency of about 22 kHz (slow response) and about 150 kHz (fast response), respectively.

[0044] The turning on/off of the CMOS switch of FIG. 6 (and thus the variation of the resistance of the filter) by the control phases slow and {overscore (slow)} may be controlled by an integrating circuit, an embodiment of which is depicted in FIG. 8.

[0045] When the signal Reg_OK, derived from VON through an inverter, is low (lack of regulation, for example because of a load current increase), the PMOS transistor driven by Reg_OK is turned on, and the current—provided by an ideal generator Iref—charges the capacitor C, whose voltage biases the gates of the NMOS transistor mirror Ma-Mb. When the voltage on the capacitor C surpasses the threshold values of the NMOS transistors Ma-Mbthe mirror turns on and the slow signal switches low, thus the short-circuiting CMOS switch of the second resistor R2 of the low pass filter of FIG. 6 closes and the regulator is set ready to track variations of VR of a higher frequency. Should the pump be in a regulated condition (Reg_OK high), the PMOS transistor controlled by Reg_OK of the integrator circuit of FIG. 8 is off. The capacitor C discharges through Ma and when the mirror turns off, the signal slow switches high reducing the cut-off frequency of the RC filter that remains sufficient to follow slower evolutions of VR. When the current delivered by the charge pump varies, also the duty-cycle of the signal Reg_OK varies and with it the average time interval in a period during which the signal slow is high. The average or “equivalent cut-off frequency” of the RC filter will range between the two extreme values.

[0046] This self adaptability of the characteristics of the low pass filter optimizes the performance of the regulator under different operating conditions, without imposing its ability to quickly react to load variations.

[0047] FIG. 9 depicts the Bode diagrams of the fed back voltages: VR and VRfilter; namely VR without compensation (curve a) and with overcompensation (curve b), and VRfilter with filtering at a minimum frequency (curve c) and at a maximum frequency (curve d). Without capacitors connected in parallel to the resistor voltage divider, frequencies over 25 kHz are cut off, while the compensation network allows them to pass (amplifying them). On the contrary, the response of the system voltage divider/RC filter is a low-pass filter, with a self adapting cut-off frequency.

[0048] FIG. 10 shows the block diagram of the regulator of the output,voltage of a charge pump according to this invention using a comparator provided with an additional input for the compensation of the offset of the regulation level, the adaptive low pass RC filter and the integrator for charging the characteristics of the filter.

[0049] Results of Simulations

[0050] Simulations of the novel regulator under “normal” operating conditions (typical: T=27° C., Vdd=Vdd,typ=1.65 V); “worst” operating conditions (slow: T=125° C., Vdd=Vdd,min=1.35 V) and “best” operating condition (fast: T=−40° C., Vdd=Vdd,max=1.95 V) have been carried out.

[0051] In FIG. 11 are shown the performances of the charge pump, respectively with a prior art regulator (old regulator) and with the regulator of this invention (new regulator) upon turning on the charge pump with no load, with a load current step of 30 μA, a ramp-up to 100 μA, a return to a loadless condition and a final turning off and discharging, for typical model conditions and at a clock frequency of 10 MHz.

[0052] The new circuit of this invention is faster in reaching a steady state and in following the variations of the load current than the known circuit, and it has a higher precision of the regulation in all conditions.

[0053] A simulation of a step response showing the functioning of the known circuit and of circuit of this invention in presence of an abrupt variations of the current absorbed by a load, from 0 to 40 μA, to 80 μA, and again to 0, is illustrated in the FIG. 12a for the prior art circuit and 12b for the novel circuit.

[0054] As may be easily observed, the known regulator reacts slower and with less precision than the novel circuit. Improving the response to step variations is even more evident in the magnified diagram of FIG. 13a for the prior art circuit and of FIG. 13b for the novel regulator of this invention.

[0055] The diagrams shown in FIG. 14a for the prior art regulator and FIG. 14b for the novel regulator, confirm that a sensible improvement of the performance is recognizable in all the three above mentioned conditions of operation: “typical”, “slow” and “fast”.

[0056] FIG. 15 illustrates the variation of a duty-cycle that the slow signal undergoes when switching from a condition of regulation with a load current of 80 μA to a condition of regulation with a zero load. It may be noticed that the filter switches from a situation in which its cut-off frequency is generally the highest frequency (in the example 150 kHz), to a situation in which it filters the high frequency clock signal with a reduced cut-off frequency (in the example of about 22 kHz).

[0057] FIG. 16 a and FIG. 16b show the waveforms of VR and of VRfilter in two different conditions, with a 40 μA load current (FIG. 16a) and with no load (FIG. 16b). The filtered signal VRfilter constitutes an offset that being input to the comparator, tends to rebalance the shift of VR from the reference value. As may be verified for both cases, the waveform of VR appears to be well centered around the value of VBG (that in the example considered is about 840 mV).

Claims

1. A regulator of the output voltage of a charge pump, comprising at least a voltage divider of the voltage present on the output node of the charge pump, a comparator comparing a certain fraction of the output voltage applied to a first input of the comparator with a constant reference voltage applied to a second input of the comparator, and outputting a certain digital signal, a logic control circuit receiving a main clock signal and outputting a timing signal of the charge pump whose frequency is determined by the state of said digital signal at every pulse of the main clock signal, and a circuit for generating control phases of the switches of said charge pump from said timing signal, characterized in that it comprises a low-pass filter, the time constant of which is automatically switched at least between two pre-established values in function of a control signal output by an integrating circuit to an input of which an inverted replica of said digital signal generated by the comparator is applied; at least a third offset signal input of said comparator connected to the output of said low-pass filter.

2. The regulator of claim 1, characterized in that said low-pass filter is an RC filter the resistance of which is constituted by a first resistor providing for a first fixed resistance of the filter and by at least a second resistor connected in series with the first resistor providing for a second additive contribution to the resistance of the filter, a capacitor, and a switch for adaptively short-circuiting said second resistor, driven by said control signal.

3. The regulator of claim 1, characterized in that said comparator has a first gain branch from which said output digital signal is derived, comprising a single NMOS transistor driven by the output of said low-pass filter and electrically connected in parallel with a plurality of NMOS transistors identical to said first single NMOS transistor but driven in common by said fraction of the output voltage; the other gain branch of the comparator being identical to said first branch, but the single NMOS transistor and the plurality of NMOS transistors are all driven by said constant reference voltage.