1. Technical Field
The present subject matter relates generally to generating voltage waveforms for testing electrical components. More specifically, the present subject matter relates to generating voltage waveforms for the purpose of injecting voltage overshoots and undershoots into electrical components.
2. Background Information
Integrated circuits (ICs) contain an ever-increasing number of electronic components. Very large scale integration (VLSI) circuits, for example, may contain millions of electrical components, most of which are transistors, on a single chip. In addition to the increasing number of electrical components, the operating frequency of such components and the minimum geometries of the technologies have also increased, introducing a variety of phenomena, such as negative bias temperature instability (NBTI) and channel hot carriers (CHC), that degrade component performance. Typically, component degradation models transform an alternating current (AC) waveform into discrete direct current (DC) parts. In these models, an effective DC signal is calculated and applied to the component for a predetermined duration depending upon the type of electrical component under test. Unfortunately, such degradation models may be unreliable and lead to conservative design techniques, such as guardbanding of the electrical component.
In accordance with at least some embodiments of the invention, a method and apparatus are disclosed that permit voltage waveforms to be generated based, in part, on a request containing a plurality of waveform parameters. A preferred embodiment comprises creating a request the comprises a plurality of waveform parameters to generate a voltage waveform, processing the request to determine a plurality of inputs based, in part, on the plurality of parameters, applying the plurality of inputs to a waveform generation circuit, and generating a voltage waveform in accordance with at least one of the parameters. The voltage waveform preferably represents a voltage overshoot or undershoot.
Notation and Nomenclature
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, various companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to.” Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.
For a more detailed description of the preferred embodiments of the present invention, reference will now be made to the accompanying drawings, wherein:
The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims, unless otherwise specified. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary, of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
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Voltage overshoots and undershoots occur in electrical components for a variety of reasons. In transistors, distributed and coupling capacitances and inductances of interconnects may readily contribute to voltage overshoots and undershoots. A transmission line mismatch in an input/output (I/O) device and a phenomenon commonly referred to as the “Miller effect” also may contribute to overshoots and undershoots in circuitry. The Miller effect is directed towards the simultaneous switching of both terminals of a capacitor, which modifies the effective capacitance between the terminals. The effective capacitance is capable of generating oscillatory noise that may cause overshoots and undershoots. When a transmission line is mismatched in an I/O device, energy may be directed back to the source, also creating oscillatory noise capable of generating overshoots and undershoots.
Although voltage overshoots and undershoots may not propagate via static complementary metal oxide semiconductor (CMOS) logic, overshoots and undershoots may contribute to noise and damage of electrical components. For example, overshoots and undershoots may lead to channel-hot-carrier (CHC) damage in n-channel metal oxide semiconductor (MOS) transistors. The channel-hot-carrier phenomenon occurs when the voltage overshoots and undershoots cause a significant increase in the magnitude of the horizontal and vertical electric fields in the channel region of MOS transistors. These elevated electric fields energize electrons and create holes in the channel, which are commonly referred to as “hot-carriers.” The hot carriers penetrate the gate oxide and cause a permanent shift in oxide charge distribution, ultimately degrading the current-voltage characteristics of the transistor.
Another degradation effect of voltage overshoots and undershoots on transistors is referred to as negative bias temperature instability (NBTI). Negative bias temperature instability occurs in p-channel MOS devices stressed with negative gate voltages at elevated temperatures. The phenomenon may result in permanent decreased drain current and an increased threshold voltage. Prolonged voltage overshoots and undershoots may lead to negative bias temperature instability in some circuitry.
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The current regulator 602 preferably comprises a voltage and temperature invariant charge pump that outputs current proportional to the frequency of the controlled oscillator 604. The clock 606 and the controlled oscillator 604 preferably operate in the gigahertz (109 hertz) frequency range in order to produce voltage waveforms that overshoot the settled value for a duration on the order of picoseconds (10−12 seconds). The clock 606 may comprise a phase locked loop (PLL) circuit, or any other type of controllable oscillator. The comparator 610 preferably possesses a fast switching to minimize the timing propagation into the programmable delay circuit 612. The programmable delay circuit 612 may comprise a chain of inverters, each inverter preferably representing approximately 20 picoseconds of delay. The frequency of the oscillator 604 may be controlled by an input 616, the period of delay caused by the programmable delay circuit 612 may be controlled by an input 618, and the frequency of the clock 606 may be controlled by an input 610.
Depending upon the voltage applied to the input 616, the oscillator 604 may produce a signal with a known frequency of oscillation. When a rising edge of the clock 606 enables the current regulator 602, the signal produced by the controlled oscillator 604 may cause the current regulator 602 to charge the V+ node of the comparator, thereby increasing the voltage of the device under test (VDUT). When the V+ node of the comparator 610 becomes greater than the reference voltage VREF applied to the V− node, a delay is instantiated by the programmable delay circuit 612. During the delay, the current regulator 602 may continue to increase the voltage of the device under test (VDUT) to a value of VDDSTRESS. After the delay, a discharge mechanism is instantiated by the discharge device 608. During the discharge, the voltage of the device under test (VDUT) is reduced to a nominal VDD value. When a falling edge of the clock 606 disables the current regulator 602, the voltage of the device under test (VDUT) is discharged to approximately zero volts. The process of charging and discharging the voltage of the device under test (VDUT) may repeat ever cycle of the clock 606.
The input 616, the input 618, the input 620, the reference voltage VREF, and the stress voltage VDDSTRESS may be used to produce a desired overshoot voltage waveform at the VDUT node that is in accordance with the waveform parameters 404 selected by a user. The current regulator 602 controls the magnitude of the overshoot via the VDDSTRESS signal, the programmable delay circuit 612 controls the duration of the overshoot via the input 618, the clock 606 controls the frequency of waveform and the duty cycle of the waveform via the input 620.
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The current regulator 902 preferably comprises a voltage and temperature invariant charge pump that outputs current proportional to the frequency of the controlled oscillator 904. The clock 906 and the controlled oscillator 904 preferably operate in the gigahertz frequency range in order to produce voltage waveforms that overshoot the settled value for a duration on the order of picoseconds. The clock 906 may comprise a phase locked loop (PLL) circuit, or any other type of controllable oscillator. The comparator 910 preferably possesses a fast switching to minimize the timing propagation into the programmable delay circuit 912. The programmable delay circuit 912 may comprise a chain of inverters, each inverter preferably representing approximately 100 picoseconds of delay. The frequency of the oscillator 904 may be controlled by an input 916, the period of delay caused by the programmable delay circuit 912 may be controlled by an input 918, and the frequency of the clock 906 may be controlled by an input 910.
Depending upon the voltage applied to the input 916, the oscillator 904 may produce a signal with a known frequency of oscillation. When a rising edge of the clock 906 enables the current regulator 902, the signal produced by the controlled oscillator 904 may cause the current regulator 902 to discharge the V− node of the comparator, thereby decreasing the voltage of the device under test (VDUT). When the V− node of the comparator 910 becomes smaller than the reference voltage VREF applied to the V+ node, a delay is instantiated by the programmable delay circuit 912. During the delay, the current regulator 902 may continue to decrease the voltage of the device under test (VDUT) to a value of VNEG. After the delay, a charging mechanism is instantiated by the charging device 908. During the charging mechanism, the voltage of the device under test (VDUT) is increased to a nominal VSS value. When a falling edge of the clock 906 disables the current regulator 902, the voltage of the device under test (VDUT) is charged to the voltage value before waveform generation. The process of discharging and charging the voltage of the device under test (VDUT) may repeat ever cycle of the clock 906.
The input 916, the input 918, the input 920, the reference voltage VREF, and the stress voltage VNEG may be used to produce a desired undershoot voltage waveform at the VDUT node that is in accordance with the waveform parameters 404 selected by a user. The current regulator 902 controls the magnitude of the undershoot via the VNEG signal, the programmable delay circuit 912 controls the duration of the overshoot via the input 918, the clock 906 controls the frequency of waveform and the duty cycle of the waveform via the input 920.
While the preferred embodiments of the present invention have been shown and described, modifications thereof can be made by one skilled in the art without departing from the spirit and teachings of the invention. The embodiments described herein are exemplary only, and are not intended to be limiting. Accordingly, the scope of protection is not limited by the description set out above.