Embodiments are generally related to a wafer inspection method for manufacturing a semiconductor device.
In-line inspection of wafers in the manufacturing process is essential for improving the manufacturing yield of semiconductor devices. As the integration degree advances in integrated circuits and memory devices, however, it becomes difficult to assign a defect detected by the in-line inspection to a structure element. The major reason of this is in the accuracy of defect position that includes deviations due to the unintentional shift of coordinates and measurement error induced in each inspection and that is relatively lowered as the miniaturization of device structure advances.
According to an embodiment, a wafer inspection method includes providing a wafer with at least one position marker; setting a care area around the at least one position marker; detecting a plurality of defects in the wafer by using a surface inspection apparatus identifying the at least one position marker as a defect, the plurality of defects including the defect corresponding to the at least one position marker; and achieving an off-set value of coordinates of the plurality of defects based on the coordinates of the defect corresponding to the at least one position marker and the coordinates of the at least one position marker.
Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.
There are cases where the dispositions of the components are described using the directions of XYZ axes shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other. Hereinbelow, the directions of the X-axis, the Y-axis, and the Z-axis are described as an X-direction, a Y-direction, and a Z-direction. Also, there are cases where the Z-direction is described as upward and the direction opposite to the Z-direction is described as downward.
The wafer 1 shown in
Step S01: Setting an inspection recipe. For instance, the controller of the inspection apparatus retrieves the design information of the semiconductor chip from a database, and sets e.g. a wafer size, and a repetition pitch and placement of chip patterns 10 formed on the wafer.
Step S02: Setting coordinates of position markers 20. The position marker 20 is placed at e.g. coordinates assigning a particular position on the wafer. Alternatively, the position marker 20 may be placed at coordinates specifying a relative position with respect to the chip pattern 10.
For instance, the position markers 20 are placed on the wafer with a pitch different from that of the chip patterns 10. The position marker 20 is placed in e.g. one of two adjacent chip patterns 10. That is, the position marker 20 is recognized as a surface defect in the surface inspection comparing two adjacent chip patterns 10.
Step S03: Setting care areas 30 (see
The care area 30 has preferably a size fitted, for example, to the viewing field of the inspection apparatus. Furthermore, preferably, the care area 30 does not include all or part of the elements of the chip pattern 10. That is, the care area 30 is set so as not to include the defects other than the surface defects corresponding to the position markers 20. This makes it easier to detect the surface defects corresponding to the position markers 20.
Step S04: Scanning the surface of the wafer 1 to detect surface defects. For instance, the SEM images, the bright-field images, or the dark-field images of two adjacent chip patterns 10 are compared. The presence or absence of defects is determined based on the difference of signal intensity exceeding a preset threshold, and then, the coordinates of the defects (in the inspection coordinate system) are recorded. Here, the inspection coordinates are identified by the inspection apparatus. For instance, the inspection coordinates include off-set of the inspection apparatus or in each inspection.
Step S05: Extracting the off-set value. For instance, the coordinates of the surface defects corresponding to the position markers 20 (in the inspection coordinate system) are extracted from the inspection data. The distance between the coordinates of the surface defects (in the inspection coordinate system) and the coordinate of the position marker 20 (in the reference coordinate system) is calculated as the off-set value of the inspection data. The off-set value is calculated as the mean value of the distance between a plurality of position markers 20 provided on the surface of the wafer 1 and the corresponding surface defects, or the median or mode value in the distance distribution. Here, the reference coordinate system is, for example, a coordinate assigned on the wafer, or the design coordinate.
Step S06: Correcting the coordinates of the defects. The coordinates of the defects other than the surface defects corresponding to the position markers 20 are corrected using the off-set value detected in step S05.
In the embodiment, the surface defects corresponding to the position markers 20 are detected in the process of surface inspection of the wafer. Thus, the off-set value in each inspection can be determined through the process of data processing in the surface inspection apparatus, or data processing using the inspection results stored in a database.
Then, the off-set value is used to correct the coordinates of the defects other than the surface defects corresponding to the position markers 20. The accuracy of defect position may be improved through this process.
As shown in
The marker patterns 5 and 7 are placed respectively so that the relative position thereof with respect to each chip pattern 10 is the same as other chip pattern 10. In the case where the marker 5 or 7 is placed in the chip pattern 10, the marker 5 or 7 is placed so that the position of marker 5 or 7 in each chip pattern 10 is the same as that in other chip pattern 10. Thus, the surface inspection apparatus may recognize the position marker 20 as a defect, which is included in the marker pattern 5.
As shown in
In the example shown in
In the following description, it is assumed for convenience that the marker pattern 5 includes at least one position marker 20 and a care area 30 therearound. The marker pattern 5 of Layer 1 includes one position marker 20. The marker patterns 5 of Layers 2-5 each include two position markers 20. The marker patterns 5 of Layers 6-15 each include four position markers 20. In the data processing procedure described later, the distance between the position markers 20 is used, which is defined along a line passing through the geometric barycenter of the four position markers 20 in each of the layers 6 to 15. Then, a distance between one pair of positon markers 20 is equal to a distance between the other pair of position markers 20.
As shown in
As shown in
As shown in
As shown in
Thus, position markers 20 with different structures can be simultaneously formed at the marker positions 1 to 4 by appropriately using the positive-type marker pattern or the negative-type marker pattern. It is possible to achieve desired detection sensitivity over the inspection apparatuses of different types. For instance, the desired detection sensitivity may be obtained at the position marker 20 of each of Layers 1-15 for at least one of the SEM image, the bright-field image, and the dark-field image.
As shown in
As shown in
Then, a wafer inspection method according to a variation of the first embodiment is described with reference to
The method for detecting the off-set value is now described with reference to the flow chart shown in
Step S11: Detecting a defect located in the care area 30. For instance,
Step S12: Calculating the distance between a pair of defects for all pairs detected in the care area 30. For instance,
Step S13: Selecting pairs of defects having a prescribed distance. For instance, all pairs of defects each having a distance in the range of Dc±Δd are selected. In the example shown in
Step S14: Calculating the differences in the X-coordinate and the Y-coordinate respectively between the center coordinates of the selected pair of defects and the coordinates of the center Cp of the position markers 20.
Step S15: Plotting the cumulative normal probability distribution of the distance between the center of the pair of defects and Cp. For instance,
Step S16: Extracting the value of ΔX at the center of the cumulative normal probability distribution as an off-set value of X-coordinate. An off-set value in the Y-direction is similarly extracted from the cumulative normal probability distribution of the difference in the Y-coordinate between the center of the pair of defects and Cp.
In this example, using the distance Dc between two position markers 20, the defect coordinates corresponding to the position marker 20 are identified, and then, the off-set value of the defect coordinates is obtained. Thus, the off-set value can be achieved even in the case where the care area 30 includes defects other than the surface defects corresponding to the position markers 20. This may improve the positional accuracy of the defects.
Then, a wafer inspection method according to a second embodiment is described with reference to
The embodiment provides e.g. a method for identifying defect coordinates in the chip pattern 10 without using the position marker 20. For instance,
For instance, the pairs having a distance in the X-direction in the range of Dp±Δd are selected (see
Furthermore, the cumulative probability distribution is plotted for each chip pattern included in each wafer. The off-set value of X-coordinate in each chip pattern is achieved similarly. Then, the defect coordinate is corrected using each off-set value in each chip pattern.
Furthermore, the cumulative probability distribution is plotted for each memory cell array included in each chip pattern. Each off-set value of X-coordinate in memory cell arrays
Ar1-Arn is achieved similarly. Then, the defect coordinates is corrected using each off-set value in each memory cell array.
The embodiment has described an example of achieving an off-set value for each wafer, for each chip pattern, and for each memory cell array, and sequentially correcting each defect coordinate. Achieving an off-set value for each wafer enables e.g. the correction of deviation of the coordinate system for each inspection over a plurality of surface inspection apparatuses. Achieving an off-set value for each chip pattern enables the correction of deviation of the coordinate system e.g. for each exposure shot of the stepper.
Furthermore, achieving an off-set value for each memory cell array enables e.g. the correction of measurement errors. For instance, the irradiation position of the electron beam in the SEM type surface inspection apparatus may be varied by electric charging. More specifically, if the components of the chip pattern are unevenly placed, their electric charging generates a potential distribution. This may deflect the electron beam and decrease the accuracy of defect coordinates. In the example shown in
The embodiment is not limited to the above example. For instance,
X-direction) at the time of wafer inspection.
Step S21: Setting an inspection recipe. For instance, a wafer size, a repetition pitch of chip patterns 10 formed on a wafer and an arrangement thereof are set in this step.
Step S22: Setting positions (marker points) for adding marker defects. For instance, the chip patterns 10 for setting marker defects are selected from a plurality of chip patterns 10 arranged on the wafer. Then, the prescribed coordinates MP in the chip pattern 10 are assigned as a marker point. The marker point specified in the chip pattern 10 is preferably a portion that can be identified with high positional accuracy, such as a corner of the pattern as shown in
Step S23: Scanning the surface of the wafer 1 to detect surface defects. For instance, the SEM images, the bright-field images, or the dark-field images are compared in adjacent chip patterns 10. The presence or absence of defects is determined based on the difference of signal intensity exceeding a preset threshold, and the coordinates of each defect are recorded.
Step S24: Adding marker defects to the inspection data. The position corresponding to a marker point of the selected chip pattern 10 is identified using e.g. the SEM image. A defect serving as a marker (marker defect) is added at the coordinates of the position. In this case, the position of the marker defect is specified in the coordinate system of the inspection apparatus (hereinafter, the inspection coordinate system).
Step S25: Determining an off-set value using the coordinates of the marker defects. For instance, the difference between the coordinate of the marker defect specified by the inspection coordinate system and the coordinate MP of the marker point specified using the coordinate system on the wafer (hereinafter, the reference coordinate system) is achieved as an off-set value. Furthermore, the achieved off-set value is used to correct the coordinates of defects for each wafer. This may improve the accuracy of defect coordinates.
In the examples described above in the first to third embodiments, the positional accuracy of the defect coordinates is improved by the off-set value of defect coordinates which is achieved using the result of wafer inspection. Thus, the failure analysis may be performed using e.g. DBB (design-based binning), and improve the manufacturing yield of semiconductor devices.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.
This application is based upon and claims the benefit of priority from U.S. Provisional Patent Application 62/304,972 filed on Mar. 8, 2016; the entire contents of which are incorporated herein by reference.
Number | Date | Country | |
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62304972 | Mar 2016 | US |