Patent Application
20080270056
1. Field of the Invention
The present invention relates to yield enhancement systems for semiconductor fabrication, and particularly to a wafer-level reliability yield enhancement system and related method.
2. Description of the Prior Art
Demand for high-performance, low-power, low-cost, mobile electronic products drives innovation in semiconductor fabrication as wafer manufacturers and foundries strive to meet those demands while maintaining high yield rate and device reliability. Ever decreasing device geometries result in tighter tolerances for each process step, be it lithography, etching, or oxidation. To increase yield, out-of-tolerance processes must be adjusted to within the allowable tolerances, and many inspection and monitoring systems are integrated into a yield enhancement system to provide engineers with data from each process, which can be correlated to defects found in electrical monitors, such as wafer acceptance testers or yield monitors.
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In general, beyond data gathered from the inspection and measurement monitors 110 and the electrical monitors 120, device reliability data is also taken. For example, the device reliability data can be time-dependent dielectric breakdown (TDDB) data, which estimates a life span of electronic devices. Traditionally, the device reliability data is not integrated into the yield enhancement system 100. Thus, the yield enhancement system 100 of the prior art is not able to provide a comprehensive correlation between device reliability and process variables. Further, data from the WAT 121 or the yield monitor 122 cannot inform the device reliability test nor can data from the device reliability test inform the WAT 121 or the yield monitor 122.
The prior art reliability test is an off-line test, and does not provide data for yield mapping. Thus, the reliability test of the prior art cannot correspond to abnormalities of in-line processes. Thus, reliability test results cannot be used for yield analysis.
According to the present invention, a yield enhancement system comprises a fabrication line comprising a plurality of semiconductor fabrication devices for fabricating a wafer, an inspection and measurement monitoring system coupled to the fabrication line for determining process data corresponding to the plurality of semiconductor fabrication devices, and a post-process testing line coupled to the fabrication line for performing in-line wafer-level testing. The post-process testing line comprises a wafer acceptance tester, a yield monitor coupled to the wafer acceptance tester, and a wafer level reliability tester coupled to the wafer acceptance tester for estimating a life span of a device on the wafer.
According to the present invention, a method of performing yield enhancement in a semiconductor fabrication process comprises obtaining reliability data, transforming the reliability data into a wafer mapping, determining a bad die location from the wafer mapping, and correlating the bad die location with a data source.
According to the present invention, a method of checking a complimentary metal oxide semiconductor (CMOS) device characteristic through an in-line wafer level reliability test comprises providing a semiconductor wafer comprising a CMOS device, utilizing an in-line wafer level reliability tester to apply a supply power to an input terminal of the CMOS device and to a power terminal of the CMOS device, and estimating a life span of the CMOS device according to an output of the CMOS device.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
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The wafer level reliability tester 223 is capable of performing a time-dependent dielectric breakdown (TDDB) test for determining the life span of the CMOS device on the wafer. Because the wafer level reliability tester 223 is coupled to the WAT 221 through the parallel data bus 340, the wafer level reliability tester 223 can receive data from the WAT 221, such as WAT_Vfb information used for calculating interface defect density, automatically through the parallel data bus 340, which speeds up process debugging. Thus, TDDB_SILC can be automatically monitored and interface defect density can be calculated immediately. Further, wafer level reliability data obtained from the wafer level reliability tester 223 can be converted to a wafer map, which increases yield enhancement through faster process debug from in-line monitoring to device reliability.
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Step 401: Start.
Step 402: Obtain wafer level time-dependent dielectric breakdown (TDDB) reliability data.
Step 403: Transform the TDDB reliability data into a wafer mapping.
Step 404: Determine a bad die location from the wafer mapping.
Step 405: Correlate the bad die location with a data source.
Step 406: End.
In the method 400 described above, correlating the bad die location with the data source (Step 405) can comprise correlating the bad die location with in-line inspection data, correlating the bad die location with wafer yield mapping data, or correlating the bad die location with etch rate data.
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Step 501: Start.
Step 502: Provide a semiconductor wafer comprising a CMOS device.
Step 503: Utilize an in-line wafer level reliability tester to apply a supply power to an input terminal of the CMOS device and to a power terminal of the CMOS device.
Step 504: Estimate a life span of the CMOS device according to an output of the CMOS device.
Step 505: End.
In the method 500, providing the semiconductor wafer comprising the CMOS device (Step 502) can comprise providing a semiconductor wafer comprising a CMOS inverter. Utilizing the in-line wafer level reliability tester to apply the supply power to the input terminal of the CMOS device and to the power terminal of the CMOS device (Step 503) comprises utilizing the in-line wafer level reliability tester to apply a supply voltage or a supply current to the input terminal of the CMOS device and to the power terminal of the CMOS device. Estimating the life span of the CMOS device according to the output of the CMOS device (Step 504) comprises estimating a time-dependent dielectric breakdown (TDDB) lifetime of the CMOS device according to the output of the CMOS device. The output of the CMOS device can comprise a current output of the CMOS device or a voltage output of the CMOS device.
In conclusion, by integrating the wafer level reliability tester 223 into the yield enhancement system through the parallel data bus 340, the WAT_Vfb data from the WAT 221 can be fed forward to the wafer level reliability tester 223 to inform the TDDB test automatically, thereby allowing for automatic monitoring of TDDB_SILC, and immediate calculation of interface defect density. Further, the wafer level reliability data obtained from the wafer level reliability tester 223 can be converted into a wafer map format for correlation with results from the process measurement and monitoring devices along with the yield monitor and the WAT. Real-time analysis according to the wafer level testing improves response efficiency from monthly data feedback to daily feedback, and changes indirect wafer mapping correlation to direct wafer mapping results. This allows for a more comprehensive yield enhancement effect, and also greatly increases efficiency of reliability test processes.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
