The present disclosure generally relates to image intensifiers used to detect low light level images, and more specifically to an electron bombarded complementary metal oxide semiconductor (EBCMOS) imager that can include further electron amplification or gain, all of which can be manufactured within multiple other image intensifier components on a wafer scale.
Low light surveillance cameras such as night vision cameras continue to advance the video display and processing capabilities of image intensifiers. Night vision cameras can include an image intensifier tube, generally known as an image intensifier. An image intensifier includes a vacuum tube into which a photocathode is spaced from a sensor anode. The photocathode detects infrared light in the form of photons from an object or image, and the image intensifier amplifies or multiples the resulting photoelectrons, or electrons, emitted from the photocathode. The anode can include a sensor that, upon receiving the electrons, produces an intensified representation of the image on a screen or display. The photocathode and the anode are typically spaced a parallel distance from each other and are supported within a vacuum housing to provide gain and facilitate the flow of electrons therebetween.
Image intensifiers generate high quality images over a wide range of light levels, including extremely low light levels encountered under starlight and lower illumination levels. The image intensifier is typically small and operates at lower electrical power, thereby making the image intensifier suitable for portable hand-held or head-mounted applications. A need exist for concurrent or simultaneous formation of multiple image intensifiers using wafer fabrication techniques. A need further exists for vacuum sealing the multiple image intensifiers at the same time to achieve consistent, readily repeatable and reliable production at a low cost. That need includes forming each component of the image intensifier on individual wafers, spacing certain wafers apart to maintain an appropriate space or gap, and then heating and evacuating the space to form multiple co-planar intensifiers on a stacked wafer scale before dicing the stacked wafers into stacked and sealed individual image intensifier die. Such need has not been conceived, or met, using conventional production techniques when forming conventional image intensifiers.
Many image intensifier cameras or, simply, image intensifiers, amplify ambient light into a useful displayed image using the photocathode. The photocathode receives the image, converts photons to electrons, and the electrons are then drawn by electrical bias toward the anode. The bias, or biasing voltage supply, is coupled between the photocathode and the anode to draw the electrons from the photocathode toward the anode. The anode can include a sensor to produce an image when the electrons strike the pixelated surface of the sensor. Thus, the anode is generally referred to as an imager anode. The photocathode and imager anode are separated by a spacer that surrounds a vacuum gap formed between the photocathode and imager anode. The imager anode can provide electron gain as the electrons are applied to the surface of the imager anode.
The imager anode preferably includes a complementary metal oxide semiconductor (CMOS) or charge-coupled device (CCD) imager sensor. The imager sensor consists of a pixelated plurality of CMOS or CCD sensors arranged in an array on an imager anode die region of an imager anode wafer. In addition to the CMOS or CCD sensors, the imager anode die can also include a primary electron multiplier. The primary electron multiplier is preferably an electron bombarded device (EBD) with one gain stage, generally known as a primary electron multiplier stage. The EBD on the imager anode imputes gain to the electrons that strike the imager anode. The multiplied electrons of the primary electron multiplier stay within the substrate of the corresponding input regions of the CMOS or CCD array of sensors.
If desired, another gain stage can be placed between the imager anode and the photocathode. This gain stage, or secondary electron multiplier stage, further increases the electron gain from the photocathode before striking the imager anode. The secondary electron multiplier is a transmission mode secondary electron (TMSE) multiplier. The TMSE is preferably spaced between the photocathode and the imager anode, all of which are contained in the vacuum housing.
The secondary electron multiplier increases the number of electrons for each electron emitted from the photocathode. One form of secondary electron multiplier is a microchannel plate, or MCP. Another form of electron multiplier can be an EBD. Similar to the photocathode and the imager anode, the EBD is manufactured as a die within a corresponding semiconductor wafer using semiconductor fabrication techniques. The EBD-type TMSE is placed between the photocathode and the CMOS or CCD image sensor of the imager anode to increase the electron gain before reaching the imager anode. The image intensifier can be formed with or without a TMSE depending on the amount of gain needed. When the electrons strike the surface of the EBD-type TMSE, the electrons are multiplied while being biased toward the imager anode. The image intensifier with an additional TMSE gain layer can therefore have two EBDs: one for the primary electron multiplier within the imager anode and another for the secondary electron multiplier within the TMSE.
An EBD is a special type of electron multiplier that utilizes advances in semiconductor manufacturing to produce doped regions in a silicon substrate to both multiply and electrically direct the electrons arriving from the photocathode. Because the EBD is produced on a semiconductor wafer, like other components of the image intensifier the EBD is a preferred electron multiplier over MCP electron multipliers. Importantly, the EBD in the secondary electron multiplier is an EBD similar to that of the primary electron multiplier so that the electron emission regions of each semiconductor wafer die of the EBD-type TMSE are aligned with corresponding electron input regions of each semiconductor wafer die of the imager anode. By using proven semiconductor fabrication technology, EBDs can be inexpensively produced in a step and repeat pattern as individual die across a wafer. If two (or more) primary and secondary electron multipliers are needed, the EBD on one wafer can be easily stacked and aligned in array or pixel registration a spaced distance from a similarly formed EBD on another wafer. Of even greater importance, the EBD of the primarily electron multiplier can be formed on the same semiconductor substrate as the CMOS image sensor to form an EBCMOS imager anode die within an EBCMOS imager anode wafer. The entire image intensifier can be formed on stacked die regions of corresponding stacked semiconductor wafers in a reliably produced wafer-scale.
The CMOS image sensor and primary EBD electron multiplier can therefore be integrated together as a EBCMOS die. The EBCMOS die are co-planar to one another as an array of imager anode die across an imager anode wafer. The EBCMOS imager anode die can be bonded to or integrated with die of an interconnect wafer, wherein each interconnect die region of an interconnect wafer includes conductive traces that extend from the imager anode output. The conductive traces can be coupled to a bus further coupled to a digital display for displaying the image sensed by the imager anode. The multiplied electrons traverse the EBD semiconductor structure between an input surface that faces the photocathode and an emission surface that faces the sensor of the imager anode. The EBD of the imager anode is coupled in a vacuum to the biasing voltage supply to draw the electrons from the emission surface of the photocathode or, if a secondary electron multiplier is used, from another EBD within the TMSE.
The image intensifier is preferably formed on a wafer scale, whereby the photocathode is spaced by an insulative spacer, and both the photocathode and the insulative spacer exist as a pair of wafers arranged parallel to each other. A wafer is defined, in the art of semiconductor fabrication, as containing a conventional circumference, diameter and thickness made by slicing individual wafers from a cylinder of material, oftentimes silicon. A wafer contains an array of die, and each die includes dopants and diffusion regions as well as one or more layers of patterned electrically conductive or insulative materials using semiconductor fabrication photolithography. The photocathode wafer and insulative spacer wafer, with an array of openings within the spacer wafer, are aligned over corresponding imager anodes. Imager anodes can be separated as die from an imager anode wafer and then bonded to an interconnect wafer. When the photocathode wafer and the openings of the insulative spacer wafer are aligned over the array of imager anodes bonded to corresponding interconnect die, pump down can occur across the entire wafer stack. Seal then occurs to produce multiple image intensifiers across a vacuum-spaced stack of multiple wafers. After pump down evacuation, getter bake, and die separation from the stacked and spaced wafers, a vacuum gap cavity is maintained between each imager anode of the plurality of imager anodes arranged across die regions of the interconnect wafer and each respective photocathode die of the plurality of photocathodes arranged across the photocathode wafer.
Thus, according to one embodiment, the image intensifier apparatus comprises a photocathode wafer comprising a plurality of photocathodes arranged co-planar to each other in an array across the photocathode wafer. An interconnect wafer is also provided, comprising a plurality of electrically separate sets of conductive traces formed in or upon the interconnect wafer. Similar to the plurality of photocathodes, the plurality of electrically separate sets of conductive traces are in interconnect die regions co-planar to each other in an array across the interconnect wafer. A plurality of imager anodes can be bonded to corresponding electrically separate sets of conductive traces within each interconnect die region. The plurality of imager anodes are arranged co-planar to each other in an array across an imager wafer. An insulative spacer wafer with openings therein can be aligned over the imager anodes, and also aligned between the interconnect wafer and the photocathode wafer. The imager anode consists of a die on the imager wafer that, after separation from the imager wafer, can be bonded to the interconnect wafer. Alternatively, the imager anode die can be integrally formed along with the semiconductor substrate die region that bears the individual set of conductive traces of the interconnect region die. Gaps or cavities can be formed within each space of a plurality of spaces formed between each imager anode of the plurality of imager anodes and each respective ones of the plurality of photocathodes. The gaps or cavities are concurrently or simultaneously evacuated to form a plurality of image intensifiers configured as an array of image intensifier arranged across three or more stacked wafers of substantially equal size: an upper photocathode wafer, a middle insulative spacer wafer, and a lower interconnect wafer, upon which an array of imager anodes are bonded to or integrated within. An imager anode can be separate from or integrated within each interconnect die region of the interconnect wafer. If the former, the imager anodes can therefore be part of each die of the interconnect wafer. If integrated within the interconnect wafer, the conductive traces of an interconnect die region are formed alongside each EBCMOS imager.
According to another embodiment, the image intensifier apparatus can further include a secondary electron multiplier wafer placed between a pair of insulative spacer wafers. The first one of the pair of insulative spacer wafers is placed between the photocathode wafer and the EBD-type TMSE secondary electron multiplier wafer. The second one of the pair of insulative spacer wafers is placed between the secondary electron multiplier wafer and the interconnect wafer. The secondary electron multiplier wafer is preferably an EBD-type TMSE semiconductor gain wafer comprising an array of co-planar EBD die, whereby each EBD die functions to increase the number of free electrons sent to the imager anode. The imager anode is preferably a CMOS imager or sensor that is appropriately biased to draw the free, multiplied electrons from the EBD die. It is noteworthy that the EBCMOS imager of the imager anode comprises a surface that, upon receipt of the free electrons, provides primary electron bombarded gain in and of itself. The EBD-type TMSE layer can provide additional (secondary) electron multiplier gain beyond that afforded by the EBCMOS imager itself.
According to yet another embodiment, an image intensifier apparatus comprises a vacuum gap between the imager anode and the photocathode. The vacuum gap is formed simultaneously with other vacuum gaps between corresponding other co-planar imager anodes bonded to the interconnect wafer and other co-planar photocathodes on the overlying photocathode wafer. If a EBD-type TMSE multiplier wafer is used comprising an array of EBD die, a first vacuum gap can exist between the EBD die of the TMSE multiplier wafer and the photocathode die, and a second vacuum gap can exist between the imager anode die and the EBD die of the TMSE multiplier wafer.
According to yet a further embodiment, a method is provided for forming an image intensifier. The method comprises bonding (or forming) a plurality of imager anodes to (or within) corresponding electrically isolated sets of conductive traces formed across an interconnect wafer. Thereafter, a plurality of openings are aligned within an insulative spacer wafer over a corresponding plurality of imager anodes. Vacuum sealing can then occur to simultaneously pump down and evacuate a plurality of photocathodes within a photocathode wafer over the corresponding plurality of imager anodes while maintaining the corresponding plurality of openings as cavities or gaps therebetween. The stacked wafers can then be separated by sawing in a direction that is perpendicular to the parallel planes formed by the vacuum sealed and spaced interconnect wafer and photocathode wafer. Scribing also occurs perpendicular to a spacer wafer having spacers between the plurality of openings to produce the image intensifier from among a plurality of concurrently produced image intensifiers.
Examples of the present disclosure are best understood from the following detailed description when read in connection with the accompanying drawings. According to common practice, the various features of the drawings are not drawn to scale, or are only shown in partial perspective. The dimension of the various embodiments are shown arbitrarily expanded or reduced for clarity. Like numerals are used to represent like elements among the drawings. Included in the drawings are the following features and elements, and reference will now be made to each drawing in which:
It should be understood at the outset that, although illustrative implementations of one or more embodiments are provided below, the disclosed systems and/or methods may be implemented using any number of techniques, whether currently known or in existence. The disclosure should in no way be limited to the illustrative implementations, drawings, and techniques illustrated below, including the exemplary designs and implementations illustrated and described herein, but may be modified within the scope of the appended claims along with their full scope of equivalents.
From the description provided herein, those skilled in the art are readily able to combine or reverse the connectivity, solder, or brazing operations, or the order by which the wafers are formed and coupled together during the pump down, vacuum bake out, or getter application methodology. While several embodiments have been provided in the present disclosure, it may be understood that the disclosed systems and methods might be embodied in many other specific forms without departing from the spirit or scope of the present disclosure. The present examples are to be considered as illustrative and not restrictive, and the intention is not to be limited to the details given herein. For example, the various elements or components may be combined or integrated in another system or certain features may be omitted, or not implemented.
In addition, techniques, systems, subsystems, and methods described and illustrated in the various embodiments as discrete or separate may be combined or integrated with other systems, modules, techniques, or methods, without departing from the scope of the present disclosure. Other items shown or discussed as coupled or directly coupled or communicating with each other may be indirectly coupled or communicating through some interface, device, or intermediate component whether electrically, mechanically, or otherwise. Other examples of changes, substitutions, and alterations are ascertainable by one skilled in the art and may be made without departing from the spirit and scope disclosed herein.
Turning now to the drawings,
The photocathode 16 can be made from semiconductor materials such as gallium arsenide, or any other materials that exhibit a photo-emissive effect. Other III-V materials can be used such as GaP, GaInAsP, InAsp, InGaAs, etc. The photo-emissive semiconductor material absorbs photons, and the absorbed photons cause the carrier density of the semiconductor material to increase, thereby causing the material to generate a photocurrent of electrons 20 passing through the photocathode 16 for emission from the output surface thereof. Photocathode 16 can be bonded to, for example, an optically transmissive wafer for structural support and environmental protection. The photocathode 16 can include an input surface 16a and an output surface 16b. When photons impinge the input surface 16a, each impinging photon 18 has a probability to create a free electron. Free electrons 20 resulting from impinging photons 18 pass through the photocathode 16 and are emitted from the output surface 16b. The output surface 16b is activated to a negative electron affinity (NEA) state in a well-known manner to facilitate the flow of electrons 20 from the output surface 16b of the photocathode 16. The peripheral surface of the photocathode 16 can be coated with a conducting surface to provide an electrical contact to the photocathode 16.
The EBD 22 multiplies the electrons emitted from the output surface 16b of the photocathode 16. EBD 22 includes a semiconductor substrate of doped regions 30, and blocking structures 32. High voltage impacts on the EBD surface create electron gain, and the doped regions 30 in the substrate and substrate surface, as well as the blocking structures 32 on the emission surface direct electrons from the output (or emission surface) surface of EBD 22, between blocking structures 32. The structure and operation of EBDs in image intensifiers for providing secondary electron multiplication of a TMSE by increasing and directing the flow of electrons, and the application of a biasing voltage supply 34 to draw electrons from photocathode 16 and increase or multiply electrons from EBD 22 is commonly known. An EBD-type TMSE is described in U.S. Pat. No. 6,836,059 (herein incorporated by reference).
The imager anode sensor 24 receives the increased number of electrons from the EBD-type TMSE 22 at an input surface 24a. The sensor of imager anode 24 is preferably an integrated circuit having a CMOS substrate and a plurality of collection wells commonly used in image intensifier tubes. Multiplied electrons 26 collected in the collection wells are processed using standard signal processing equipment for CMOS sensors to produce an intensified image signal that is sent through an output bus 25 to electronic display 14. In the preferred embodiment, the sensor is a die of a semiconductor wafer containing an array of CMOS integrated circuit pixel sensors arranged across a die of an imager anode 24. The readout of the sensed multiplied electrons 26 are controlled by timing and control circuits, and the signals can be processed by processors of conventional design. The processors can comprise analog-to-digital converters arranged in each column, and the signals are read out by a column select unit and placed on corresponding lines of bus 25. The array of pixels can be a photodiode type pixel structure. When reverse biased, current will flow through the photodiode with incident light creating photocurrent. The photocurrent is sent in corresponding lines of bus 25 to render an intensified image 28 on display 14. The structure and operation of an electron bombarded CMOS imager is described in U.S. Pat. No. 6,657,178, herein incorporated by reference.
Imager anode 24 is biased to draw the multiplied electrons 26 from the output or emission surface of the EBD-type TMSE 22. Within imager anode 24, along with the array of CMOS sensors, is a primary electron multiplier that is preferably an EBD. The primary electron multiplier EBD can be arranged within the input surface 24a of imager anode 24, and the CMOS sensor array can be arranged within the output surface 24b of imager anode. The primary electron multiplier EBD within the input surface 24a is similar to EBD 22 in the secondary electron multiplier, or TMSE, in it provides electron multiplication. However, instead of it providing electron multiplication from photocathode 16 to imager anode 24 as in the EBD-type TMSE 22, the EBD within the input surface 24a provides electron multiplication from the input surface 24a to the output surface 24b of imager anode 24.
After the imager anode 24 has been run through the electrical interconnection process, it is subjected to a vacuum bake-out as shown by arrow 49 before the housing is sealed around the image intensifier 10. The space between the photocathode 16, or photocathode die 16 and the bonded imager anode 24, or imager anode die 24, can be evacuated below one atmosphere before the lateral plates 44 surrounding all four sides of the imager anode 24 are sealed between the photocathode 16 and imager anode 24. Getter material can be placed on the inward-facing surfaces of spacers 44, for example, and the getter material can be activated during the bake-out process. As the vacuum is created between the photocathode 16 and the imager anode 24, the getter remains to assists in prolonging life of the image intensifier 10 by adsorbing residual gases from all of the components within the vacuum.
To increase gain in the vacuum gap or cavity formed between imager anode 24 and photocathode 16, EBD-type TMSE 22 can be placed in the vacuum gap and an appropriate bias is applied between the photocathode 16 and TMSE 22, as well as between TMSE 22 and imager anode 24. Placement of TMSE 22 is optional depending on the amount of electron multiplication and gain is needed. Given the use of EBD-type TMSE 22 is optional, it is therefore shown in phantom with a dashed line. However, to increase gain in order to overcome limitations of conventional electron bombarded CMOS (EBCMOS) image intensifiers, EBD-type TMSE 22 as a secondary electron multiplier is used. Conventional EBCMOS imager gain is limited by the maximum voltage in the vacuum gap so as not to produce x-rays. Placing EBD 22 therein increases free electrons and gain in the vacuum gap without producing x-rays. Doping in the semiconductor substrate of the EBD 22 helps increase the number of electrons from the input surface into the semiconductor substrate, and through the semiconductor substrate. Inhibiting the recombination of electrons at the input surfaces ensures that more electrons flow through the semiconductor substrate to the emission surface of the EBD-type TMSE 22 as described in commonly assigned U.S. Pat. No. 6,836,059, herein incorporated by reference.
Alternatively, on the front-side surface of each imager anode 24, either within and part of, or bonded to, an interconnect wafer, are wirebonds that exist outside the vacuum cavity and shielded from the high voltage field therein. If the imager anode is bonded to the interconnect wafer, according to one embodiment, the conductive traces within the interconnect wafer can extend to the backside surface of each die within separately diced interconnect die regions 54 of interconnect wafer 64, where pins 47 shown in
Each imager anode 24 taken as a die from an imager anode wafer, is bonded to a corresponding set of conductive traces within region 54 of interconnect wafer 64. The interconnect die regions 54 are shown aligned below openings 52, wherein openings exist between insulative spacer die areas 72 repeated across insulative spacer wafer 62. Regions 54 are coplanar with each other across interconnect wafer 64 a parallel spaced distance below yet aligned with photocathode die coplanar regions 50 of photocathode wafer 60. Openings 52 within insulative spacer wafer 62 are aligned between overlying regions 50 of photocathode wafer 60 and underlying imager anodes 24 bonded within regions of 54 of interconnect wafer 64. The formation of the stacked wafers and the subsequent vacuum, or vacuum combined with bake out, provide a wafer scale manufacturing process for concurrently generating an array of co-planar image intensifiers from which a plurality of EBCMOS vacuum image intensifiers are formed once the array is diced and the die are separated from each other.
The openings 52 within insulative spacer 72 form the high voltage vacuum gaps 70 between the overlying photocathodes 50 and the underlying imager anode 24 bonded to the set of conductive traces upon and within interconnect region die 54. The spacer 72 around each opening 52 is formed when the insulative spacer wafer 62 is cut along the dotted line 74 when dicing and forming the vacuum sealed, stacked set of dies. When the high vacuum envelope is created at the wafer scale, by sealing in a vacuum the entire set of stacked wafers, an array of multiple image intensifiers 10 are formed at the same time. When diced into individual intensifiers 10 at a later time, multiple image intensifiers 10 are formed, as shown in
As noted in
In
In
Alternatively, as shown in
The photocathode 50 die central point, the EBD-type TMSE 22 die central point, the imager anode 24 die central point, and the interconnect region 54 die central point are each aligned on the central axis 74. Moreover, the central axis 74 is shown as the central axis of the formed image intensifier 10. Not only are each die of the same size and dimension, but the central point on the upper and lower planar surfaces of each die align with and are on the central axis 74 to ensure proper operation of the formed image intensifier 10. For example, if there is any offset greater than, for example, 50 percent of the pixel pitch from the central axis, the array of primary and secondary electron multipliers will not align with each other and they will also not align with the CMOS sensor array within the imager anode 24.
As used herein, “about,” “approximately” and “substantially” are understood to refer to numbers in a range of numerals, for example the range of −10% to +10% of the referenced number, preferably −5% to +5% of the referenced number, more preferably −1% to +1% of the referenced number, most preferably −0.1% to +0.1% of the referenced number.
Furthermore, all numerical ranges herein should be understood to include all integers, whole or fractions, within the range. Moreover, these numerical ranges should be construed as providing support for a claim directed to any number or subset of numbers in that range. As used herein and in the appended claims, the singular form of a word includes the plural, unless the context clearly dictates otherwise. Thus, the references “a,” “an” and “the” are generally inclusive of the plurals of the respective terms.
Without further elaboration, it is believed that one skilled in the art can use the preceding description to utilize the claimed inventions to their fullest extent. The examples and aspects disclosed herein are to be construed as merely illustrative and not a limitation of the scope of the present disclosure in any way. It will be apparent to those having skill in the art that changes may be made to the details of the above-described examples without departing from the underlying principles discussed. In other words, various modifications and improvements of the examples specifically disclosed in the description above are within the scope of the appended claims. For instance, any suitable combination of features of the various examples described is contemplated, including the orientation of the photocathode above, below, or spaced to the right or left of the imager anode. Depending on the orientation of the image intensifier relative to the image being detected, the photocathode relative to the imager anode can change provided the photocathode is between the imager anode and the image.
The present application is based on, claims priority from, and is a continuation of pending Patent Application Ser. No. 63/058,256, filed Jul. 29, 2020, the disclosure of which is incorporated herein by reference in its entirety.
Number | Date | Country | |
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63058256 | Jul 2020 | US |