Patent Application
20140145294
Aspects of the present disclosure relate to apparatuses, devices, and methods for separation of a wafer.
Integrated circuits (ICs) are typically produced by forming a plurality of ICs on a semiconductor substrate, such as silicon. The ICs include one or more layers formed on the substrate (e.g., semiconductor layers, insulative layers, and metallization layers). The individual ICs are separated by lanes. The finished ICs on the wafer are then separated into individual ICs by, for instance, sawing the wafer along the lanes. Separation of the wafer into individual ICs may be referred to as dicing. Sawing may be performed using various mechanical cutting and laser cutting methods. Mechanical cutting tools tend to cause chipping of the backside of a substrate. Laser cutting tends to cut unevenly in metallization layers formed on a front-side of the substrate.
Aspects of the present disclosure relate to separation of ICs on a silicon wafer. In one embodiment, a method is provided for dicing a wafer into separate ICs. The wafer includes a silicon substrate and metallization layer(s) on a front-side of the silicon substrate. Channels are formed in the metallization layer(s) along respective lanes. The lanes are located between ICs and extend between a front-side of the metallization layer(s) and a backside of the silicon substrate. After a backside of the silicon substrate is thinned, crystalline structure of portions of the silicon substrate located within the lanes are modified by applying a laser via the backside of the silicon substrate. The portions are offset from the backside of the silicon substrate and from the metallization layer(s).
The ICs are separated along the lanes by expanding the silicon substrate while using the changed crystalline structure and the channels to propagate cracks in the silicon substrate along the lanes, and mitigate cracking of the silicon substrate and metallization layer in regions outside of the lanes.
In another embodiment, an IC wafer configured to facilitate separation of the wafer into individual ICs is provided. The wafer includes a silicon substrate and metallization layer(s) on a front-side of the silicon substrate. Channels are formed in the metallization layers along respective lanes. The lanes are located between a plurality of ICs on the wafer and extend between a front-side of the metallization layers and a backside of the silicon substrate. A plurality of portions in the silicon substrate, located within the lanes, have a crystalline structure that is different from a crystalline structure of the silicon substrate outside of the lane. The plurality of portions in the silicon substrate and the channels are configured to propagate cracks in the silicon substrate along the lanes and mitigate propagation of cracks outside of the lanes during expansion of the IC wafer.
While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure including aspects defined in the claims.
Aspects of the present disclosure may be more completely understood in consideration of the detailed description of various embodiments of the present disclosure that follows in connection with the accompanying drawings, in which:
While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure including aspects defined in the claims. In addition, the term “example” as used throughout this application is only by way of illustration, and not limitation.
Aspects of the present disclosure relate to separation of ICs on a semiconductor wafer. For example, various embodiments are directed to separating ICs in a wafer having a silicon substrate as a back-side of the wafer, and one or more metallization layers/active regions on the substrate on a front-side of the wafer.
Some embodiments are directed to a method for separating such a wafer into individual ICs. Channels are formed in the one or more metallization layers on a front-side of the wafer along respective lanes along which the ICs are to be separated. These (separation) lanes are located between ICs and extend between a front-side of the wafer at the metallization layer(s), and a backside of the wafer at the silicon substrate. After forming the channels, the backside of the silicon substrate is thinned, and laser pulses are applied via the backside of the silicon substrate to change the crystalline structure of the silicon substrate along the lanes. This change in the silicon structure weakens the silicon in the lanes. The changed portions in the silicon substrate and the channels facilitate the propagation of cracks in the silicon substrate along the lanes during expansion of the wafer, while mitigating propagation of cracks outside of the lanes. With this approach, wafer separation can be achieved while mitigating issues that can arise from the formation of cracks, and as discussed above.
In various embodiments, the changed portions of the silicon substrate are located within the lanes at various depths in the silicon substrate. For instance, in some embodiments, the changed portions may be offset from one or both of the metallization layer and from a backside of the silicon substrate. The figures depict exemplary embodiments in this regard. The positioning of the changed portions may be set to achieve desired structural support within the substrate (via unchanged portions in the lanes) and/or achieve a desired propagation of cracks during expansion of the wafer.
In various embodiments, the crystalline structure in the silicon substrate is changed as discussed above by applying laser pulses to the silicon substrate via the backside to first melt and then solidify the silicon substrate along the lanes. In some embodiments, the laser pulses are focused to converge at a depth in the silicon substrate at which the portions to be changed are located. In some embodiments, crystalline structure of the silicon substrate may be changed at multiple (e.g., >1) depths in the silicon substrate. For instance, in one embodiment, a first laser is used to modify a crystalline structure of portions located at a first depth in the silicon substrate and a second laser is used to modify a crystalline structure of portions located at a second depth in the silicon substrate. The two depths may be separated by a layer in the silicon substrate at which the crystalline structure of the silicon is not changed. Modification of the crystalline structure at different depths along the lanes of the silicon substrate may be desirable, e.g., for substrates that are thicker than 150 μm or composed of low ohmic material. While the embodiments are not so limited, for ease of explanation, the disclosed examples are primarily described with reference to modification of a crystalline structure at a single depth in the silicon substrate.
One or both of the duration of the laser pulses and interval between the laser pulses are set to suit particular embodiments. In some implementations, sequential laser pulses are applied with a delay between the pulses that is sufficient to prevent the temperature of the substrate from exceeding a threshold that would damage the integrated circuits. In these and/or other implementations, sequential laser pulses are applied with a delay that is set to control a rate at which the melted portions of the silicon are solidified. For example, a first rate of laser pulsing may be applied to melt the silicon while ensuring that ICs therein are not damaged. After melting, a different rate of laser pulsing (i.e., with an increased delay) may be applied to allow the melted silicon to solidify, while controlling the rate of solidification (e.g., by controlling the rate of cooling).
In some embodiments, the channels formed in the metallization layer are formed at a depth sufficient to achieve desired propagation of cracks in the metallization layer during wafer expansion. As explained in more detail in the following, the channels in the metallization layer assist to create a weak point in the metallization layer at which cracks will form in the metallization layer when subjected to expansive stresses during wafer expansion. In some embodiments, the formed channels have a depth that is less than a thickness of the metallization layer. Due to the portion of the metallization layer retained in the channels, a larger expansion force must be exerted before cracks are formed in the channels of the metallization layer. As a result, for some wafer structures, cracks will propagate more evenly in the silicon substrate after the stresses cause the metallization layer to break in the channels. In some embodiments, the channels are formed to have a depth that is 90% of a thickness of the metallization layer.
In some embodiments, various layers of support tape are placed on the substrate and/or metallization layer to support the wafer during processing and expansion of the wafer. For instance, in some embodiments, one or more layers of support tape are placed on the metallization layer prior to thinning the backside of the silicon substrate. Similarly, in some embodiments, after applying the laser to change the crystalline structure of the portions of the silicon substrate and prior to wafer expansion, a layer of support tape is place on the backside of the silicon substrate.
For ease of explanation, examples are primarily described with reference to a wafer comprising a silicon substrate and a metallization layer on the front-side of the wafer. However, the embodiments are not so limited. It is understood that a wafer to be diced may include other materials, layers and/or structures including, but not limited to, semiconductor layers, dielectric layers, isolation layers, metallization layers, and passivation layers.
In some embodiments, the crystalline structure is changed in the portions of the silicon substrate by applying pulses of a laser to the silicon substrate to melt silicon in the target portion and then quickly solidify the melted silicon. Due to the rate at which the silicon recrystalizes, the silicon has a different crystalline structure than that of the unchanged silicon substrate. As a result of the non-uniform crystalline structure, the silicon substrate is weakened at the changed portions. The duration between sequential laser pulses may be adjusted to control the rate at which the melted silicon recrystalizes. The duration between sequential laser pulses may also be adjusted to prevent the temperature of the substrate from exceeding a threshold that may damage the integrated circuits.
In some implementations, the laser pulses may be focused to converge as a point in the silicon substrate between the metallization layer and the backside of the silicon substrate. In this manner, the changed portion of the silicon may be limited to a region along the lanes that is offset from the front-side and the backside of the silicon substrate. The unchanged portions in the lanes adjacent to the metallization layer and backside of the substrate provide support for the wafer prior to expansion.
The wafer in
The ICs are separated by expanding the wafer to form cracks along the lanes.
In some embodiments, the channels formed in the metallization layer have a depth that is less than a thickness of the metallization layer. For instance, for a metallization layer of 10 μm thickness, the channels may have a depth that is less than or equal to 9 μm. Because a portion of the metallization layer is retained in the cutting layers, a larger expansion force must be exerted before cracks are formed in the channels of the metallization layer. Due to this larger force, cracks will propagate more evenly in the silicon substrate after the stresses cause the metallization layer to break in the channels.
The embodiments are thought to be applicable to a variety of applications, which involve dicing of semiconductor wafers. Other aspects and embodiments will be apparent to those skilled in the art from consideration of the specification. While the present disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in further detail. It should be understood that the intention is not to limit the disclosure to the particular embodiments and/or applications described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure.
