Patent Application
20070181420
1. Field of the Invention
The present invention relates generally to an apparatus for manufacturing a semiconductor device and, more particularly, to a wafer stage having an encapsulated central pedestal plate, which is used in a pre-clean chamber of a PVD or CVD cluster tool.
2. Description of the Prior Art
Physical vapor deposition (PVD) and chemical vapor deposition (CVD) processes are known in the art. A PVD or CVD cluster tool typically comprises multiple chambers including a pre-clean chamber, in which a pre-clean process is performed to remove undesirable surface oxides such as silicon dioxide or metal oxides from the surfaces of the substrates. The pre-clean process is ordinarily carried out before the substrates are subjected to the primary PVD or CVD process.
The uppermost surface 26 of the quartz insulator plate 12 is an annular perimeter area located around the central pedestal plate 14. The central pedestal plate 14 further comprises an annular perimeter surface 28 formed around the uppermost surface 26 with a height slightly lower than the surface 26. A gap 32 is formed between the uppermost surface 26 of the quartz insulator plate 12 and a bottom surface of the wafer 20.
The central pedestal plate 14 is a part of a process kit that system operators periodically clean during routine maintenance. It is desirable that a process kit has a long useful lifetime, so that the downtime of the system will be a small percentage of the overall processing time. One disadvantage of the above-described prior art is that the pre-clean process can cause particles to accumulate in the gap 32, and on the uppermost surface 26 and the annular perimeter surface 28 of the quartz insulator plate 12. A seam 36 formed between the central pedestal plate 14 and the quartz insulator plate 12 deteriorates the particle problem.
In light of the above, there is a need in this industry to provide an improved wafer stage of a pre-clean chamber that is capable of minimizing particle contamination in a pre-clean process prior to the primary CVD or PVD process. Further, it would be desirable to extend the specified lifetime of a process kit.
It is one object of the present invention to provide an improved wafer stage having an encapsulated central pedestal plate, which is used in a pre-clean chamber of a PVD or CVD cluster tool.
According to the claimed invention, a wafer stage for placing a wafer in a processing chamber. The wafer stage includes a bottom insulator plate secured on a bottom portion of the processing chamber; a central pedestal plate mounted on the bottom insulator plate; and a removable top insulator cover having a chamber fittingly accommodating the central pedestal plate and the bottom insulator plate, wherein the top insulator cover has a flat top surface for placing the wafer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:
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According to the preferred embodiment, both the bottom insulator piece 112 and the top insulator piece 130 are made of quartz. However, other suitable insulating materials may be employed. In another case, the bottom insulator piece 112 and the top insulator piece 130 may be made of different insulating materials.
The top insulator piece 130 functions as a cover that has a chamber 116 fittingly accommodates the central pedestal plate 114 and the bottom insulator piece 112 such that plasma is not in direct contact with the central pedestal plate 114 and the bottom insulator piece 112 during a pre-clean process. By doing this, the central pedestal plate 114 can be kept in very clean condition all the time and thus the period for changing the central pedestal plate 114 is extended.
It is one salient feature of the present invention that the thickness t of the top insulator piece 130 between the wafer and the central pedestal plate 114 is preferably less than 5 millimeters in order not to obstruct the generation of plasma or interfere the output of a bias RF power provided through the central pedestal plate 114.
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Further, the central pedestal plate 114 and bottom insulator piece 112 have respective central through holes 158 and 168. The central pedestal plate 114 and bottom insulator piece 112 are secured to the base portion 110 by using a screw 178 via the through holes 158 and 168. The screw 178 is electrically connected to a power supply that provides the central pedestal plate 114 with desired bias power in a pre-clean process.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
