In 2012, NASA sponsored research and design efforts related to an RF (Radio Frequency) channel using a microstrip (SMA launching excitation) with a perforated ground plane for a cryogenic application. Teams from various Universities and NASA participated in this research, design and prototype effort. A device was eventually designed and was able to achieve isolation levels of about 30 dB over a relatively narrow frequency range and perform at temperatures of 297 K and 77 K.
What is needed is an RF transmission structure for cryogenic applications with a larger frequency band of operation, a better impedance match and improved channel-to-channel isolation.
According to one aspect of the disclosure, an RF signal interconnect device comprises a first dielectric substrate having a first surface and a second surface and first and second ends; a plurality of conductive traces provided on the first surface of the first dielectric substrate, each trace having first and second ends, wherein each of the first and second ends has a predetermined shape; a second dielectric substrate disposed on the first surface of the first dielectric substrate, the second dielectric substrate having first and second ends respectively aligned with the first and second ends of the first substrate, wherein the second dielectric substrate is configured so as not to cover the first and second ends of the conductive traces, whereby the first and second ends of the traces are exposed; a first connector coupled to the first ends of the first and second dielectric substrates; a first plurality of conductive pin assemblies disposed in the first connector, each conductive pin assembly coupled to a respective first end of a conductive trace where the conductive trace is not covered by the second dielectric substrate, wherein the first connector is configured to define a respective isolating chamber about each of the first ends of the conductive traces.
In another aspect of the present disclosure, an RF signal interconnect device comprises a signal carrying structure. The signal carrying structure comprises a first dielectric substrate having a first surface and a second surface; a plurality of conductive traces provided on the first surface of the first dielectric substrate, each trace having first and second ends, wherein each of the first and second ends has a predetermined shape; and a second dielectric substrate disposed on the first surface of the first dielectric substrate, wherein the second dielectric substrate is configured so as not to cover the first and second ends of the conductive traces, whereby the first and second ends of the traces are exposed. In addition; a first connector, coupled to the signal carrying structure, comprises an upper shell portion; a plurality of dividing walls provided in the upper shell portion and defining a plurality of cavities; and a first plurality of conductive pin assemblies, each pin assembly arranged in a respective upper shell portion cavity and coupled to a respective first end of a conductive trace where the conductive trace remains exposed through the second dielectric substrate, whereby a respective isolating chamber about the first ends of the conductive traces is provided.
Various aspects of the disclosure are discussed below with reference to the accompanying Figures. It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn accurately or to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity or several physical components may be included in one functional block or element. Further, where considered appropriate, reference numerals may be repeated among the drawings to indicate corresponding or analogous elements. For purposes of clarity, not every component may be labeled in every drawing. The Figures are provided for the purposes of illustration and explanation and are not intended as a definition of the limits of the disclosure. In the Figures:
In the following description, details are set forth in order to provide a thorough understanding of the aspects of the disclosure. It will be understood by those of ordinary skill in the art that these may be practiced without some of these specific details. In other instances, well-known methods, procedures, components and structures may not have been described in detail so as not to obscure the aspects of the disclosure.
It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the drawings as it is capable of implementations or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description only and should not be regarded as limiting.
Certain features, which are, for clarity, described in the context of separate implementations, may also be provided in combination in a single implementation. Conversely, various features, which are, for brevity, described in the context of a single implementation, may also be provided separately or in any suitable sub-combination.
It should be noted that, where used, “top,” “bottom,” “upper,” “lower,” etc., are merely for explaining the relative placement of components described herein. These relative placement descriptions are not meant to limit the claims with respect to a direction of gravity or a horizon.
Generally, and as will be described in more detail below, aspects of the present disclosure provide an RF signal interconnect device that provides for RF high speed signal communication within a system at cryogenic temperatures. The device is sized to fit within small packaging requirements, e.g., a 101.6 μm vertical stack. Further, the device is flexible to allow for bending during operation and operates over an ultra-wide frequency band with return loss and isolation between channels that exceeds that which had been previously demonstrated. Advantageously, the device is structured to convert, from a connector on one end to a connector on the other end, from a coaxial TEM (Transverse Electromagnetic) mode of transmission to a microstrip mode, to a hybrid mode, and to a strip-line mode, sequentially. A transitional cavity between the coaxial and microstrip structures serves to minimize unwanted high order mode excitations. Further, combinatory signals, i.e., received and transmitted signals or bi-directional signals, are supported.
In addition, as will be described, the device uses flexible polyimide dielectric materials, for example, Kapton® polyimide available from DuPont, to fabricate the ultra-wide frequency band RF signal interconnect device for a cryogenic application. In one use, the interconnect device is deployed within a communication system to provide a plurality of RF combinatory signals for transmission and reception prioritization. In one non-limiting example, a primary frequency band of operation, impedance match and isolation of interest was established to be DC to 10 GHz, nominally 4 to 9 GHz, −15 dB, and 50 dB, respectively. For operation at very low cryogenic temperatures of about 4 K, the device is implemented with Niobium conductors.
Referring now to
The signal carrying structure 104 includes a first dielectric substrate 204 as shown in
The first and second ends 208, 212 of the first dielectric substrate 204 include a plurality of slots 304 that are defined in each respective end. Each pair of adjacent slots 304 further defines a trace tab 308 which will be described below.
A plurality of conductive traces 404 are provided on a first surface 408 of the first dielectric substrate 204 as shown in
The traces 404 may be provided on the first surface 408 by any one of known deposition processes including, for example, silk-screening and sputtering.
As shown in
Generally, each trace 404 has a constant width TW along most of its length, excluding a trace launch portion 604 as depicted in
The signal carrying structure 104 includes a second dielectric substrate 704 that generally has a same length and shape as the first dielectric substrate 204. The second dielectric substrate 704 may be made from Kapton EN200 or Kapton HN500 with respective thicknesses of 0.002 in and 0.005 in for operation at very low temperatures, that is, in cryogenic or superconducting conditions. Alternately, the second dielectric substrate 704 may be made from Kapton Pyralix AP if not operating at superconducting temperatures. The ends 708, however, of the second dielectric substrate 704 are not configured in the same manner as the ends 208, 212 of the first dielectric substrate 204 as is shown in
Each end 708 includes a plurality of slots 712 that are positioned to align with the slots 304 of the first dielectric substrate 204 when the second dielectric substrate 704 is placed upon it. A generally V-shaped, or triangular, notch 716 is defined between each slot 712 and positioned to align with a respective trace tab 308 of the first dielectric substrate 204.
As part of a stack of components of the signal carrying structure 104, the second dielectric substrate 704 is positioned over the first dielectric substrate 204, as is shown in
The arrangement of the ends 708 of the second dielectric substrate 704 over the respective ends of the first dielectric substrate 204 creates an opening 804 where a portion of the first surface of the first dielectric substrate 204 remains exposed, as shown in
Referring now to
The trace launch 604 starting from the end of the device 100 i.e., left-to-right in
A terminal end of the trace launch 604 has a triangular notch 608 defined therein that exposes the first dielectric substrate 204 underneath. The notch 608 has a width J of 0.010±0.001 in and a height L of 0.0018±0.0005 in, as shown in
A cross-section of the “stack-up” of the signal carrying structure 104 along line A-A, shown in
In one non-limiting method of manufacturing the signal carrying structure 104, the lower shield 1112 and a layer of conducting material are deposited on the first dielectric substrate 204. The conducting material is then etched, resulting in the conductors 404. The second dielectric substrate 704 is provided with the first protective layer 1108 when the waveguide features are created and is then laminated to the first dielectric substrate 204. Subsequently, the shape of the cable is created after lamination by a cutting operation.
The two end connectors 108 are the same and include an upper shell 1204 and a lower shell 1208 as shown in
Each coaxial pin assembly 1304 as shown in
As shown in
The upper shell 1204 includes a plurality of baffles 1704 and back walls 1708 that define a cavity 1712 as shown in
Referring to
The conductive traces 404 run from a respective trace launch 604 at the first end 208 to a respective trace launch 604 at the second end 212. Referring back to
Generally, the spacing C between centers of trace launches 604 is greater than the spacing T of 0.0320±0.0002 between traces 404 at that portion of the device 100 where the traces 404 are running in parallel to one another.
Advantageously, the device 100 provides a reduced parasitic thermal load by reducing the cable width from a point 412-1 to a point 412-2, as shown in
The present disclosure is illustratively described above in reference to the disclosed implementations. Various modifications and changes may be made to the disclosed implementations by persons skilled in the art without departing from the scope of the present disclosure as defined in the appended claims.
This invention was made with Government support. The Government has certain rights in the invention.
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9418715 | Aug 1994 | WO |
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