Claims
- 1. In an integrated circuit, a method for generating first and second internal supply voltages for powering circuits of the integrated circuit, and a substrate bias voltage for the integrated circuit, the method comprising the steps of:
- receiving, within the integrated circuit, an input supply voltage having a magnitude that is within a wide power supply range;
- generating and outputting a first internal supply voltage for use by on-chip low voltage circuits; and
- generating and outputting, for use by on-chip high voltage circuits, a second internal supply voltage that is based upon and higher than said first internal supply voltage and that is substantially constant and substantially independent of variations in the input supply voltage; and
- generating a substrate bias voltage based on the first internal supply voltage.
- 2. The method of claim 1 wherein said step of generating and outputting a first internal supply voltage includes:
- generating a reference voltage; and
- processing said input supply voltage and said reference voltage to generate said first internal supply voltage.
- 3. The method of claim 2 wherein said first internal supply voltage is a low voltage signal.
- 4. The method of claim 1 wherein said step of generating a second internal supply voltage includes converting said first internal supply voltage to said second internal supply voltage which is a high voltage output.
- 5. The method of claim 1 further including the steps of providing said first and second internal supply voltages to low voltage circuits and high voltage circuits, respectively, located in the same integrated circuit.
- 6. A method for powering an integrated circuit by generating internal supply voltages comprising the steps of:
- receiving wide range input supply voltage,
- generating a reference voltage from said input supply voltage,
- processing said input supply voltage and said reference voltage to generate a first internal supply voltage that is substantially independent of variations in the input supply voltage,
- generating a second internal supply voltage that is based upon said first internal supply voltage and that is substantially constant and substantially independent of variations in the input supply voltage, and
- driving substantially all circuitry on said integrated circuit with said first and second internal supply voltages.
- 7. The method of generating internal supply voltages of claim 6 further including the step of providing said first internal supply voltage to low voltage circuits.
- 8. The method of generating internal supply voltages of claim 6 further including the step of providing said second internal supply voltage to high voltage circuits.
- 9. The method of generating internal supply voltages of claim 6 further including the step of generating, from one of said internal supply voltages, a negative voltage which is coupled to the substrate of the semiconductor device to maintain the voltage at the substrate.
- 10. The method of claim 6 further including the step of generating a negative voltage based upon said first internal supply voltage and applying the negative voltage to bias the substrate of the integrated circuit.
Parent Case Info
This application is a divisional of U.S. application Ser. No. 08/003,450, filed on Jan. 12, 1993, U.S. Pat. No. 5,483,152.
US Referenced Citations (6)
Foreign Referenced Citations (3)
Number |
Date |
Country |
3923632 |
Nov 1990 |
DEX |
4115082 |
Nov 1991 |
DEX |
2248357 |
Jan 1992 |
GBX |
Non-Patent Literature Citations (1)
Entry |
Noda et al., "A Boosted Dual Word-line Decoding Scheme For 256 Mb DRAMS" Symposium on VLSI Circuits, Digest of Technical Papers, (1992). |
Divisions (1)
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Number |
Date |
Country |
Parent |
03450 |
Jan 1993 |
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