Feth et al., "High-Density Cell Layout Design for VLSI Semiconductor Chips", IBM Technical Disclosure Bulletin, vol. 27, No. 11, pp. 6741-6744, 1985. |
Curtin et al., "Chip-Redundant Wiring Technique", IBM Technical Disclosure Bulletin, vol. 27, No. 12, pp. 7225-7226, 1985. |
Bajuk et al., "Borderless Gate Contacts for CMOS Applications", IBM Technical Disclosure Bulletin, vol. 32, No. 3B, pp. 71-73, 1989. |
Ishikawa et al., "Compaction Based Custom LSI Layout Design Method", IEEE Computer Society, Nov. 18-21, 1985, IEEE International Conference on Computer-Aided Design, pp. 343-345. |
Anderson et al., "Chip Design Exclusively by Programs", IBM Technical Disclosure Bulletin, vol. 32, No. 3B, pp. 417-418, 1989. |
R. S. Rutter, "Method to Improve Chip Wiring", IBM Technical Disclosure Bulletin, vol. 32, No. 4B, pp. 290-293, 1989. |
Dennean et al., "Wiring Machine", IBM Technical Disclosure Bulletin, vol. 24, No. 11A, pp. 5377-5383, 1982. |
Berndlmaier et al., "Optimizer Chip Cell Organization", IBM Technical Disclosure Bulletin, vol. 21, No. 4, pp. 1463, 1978. |
Hauge et al., "Procedure for Hierarchical Chip Physical Design", IBM Technical Disclosure Bulletin, vol. 28, No. 5, pp. 1981-1985, 1985. |
Coppersmith et al., "Improved Local Wiring of Movable Terminals in VLSI Chips", IBM Technical Disclosure Bulletin, vol. 26, No. 12, pp. 6315-6317, 1984. |
Kurtzberg et al., "Estimating Chip Wirability by Routing Configuration Averaging", IBM Technical Disclosure Bulletin, vol. 26, No. 5, pp. 2625-2633, 1983. |