Patent Application
20050199913
1. Field of the Invention
The invention relates to a semiconductor memory, and more particularly, to a semiconductor memory having FinFET elements.
2. Description of the Related Art
Conventional non-volatile semiconductor memory elements exist in a multiplicity of different embodiments, e.g., PROM, EEPROM, FLASH EEPROM and SONOS, depending on the application. These various embodiments differ in particular in terms of erasure option, programmability and programming time, retention time, storage density and also in terms of their production costs. There is a particular need for high-density and inexpensive FLASH semiconductor memory elements. Known embodiments are in particular so-called NAND and ETOX memory cells, but the storage density thereof requires more than 4F2, where F is the smallest semiconductor memory feature size occurring in the process.
The publication by B. Eitan et al. “NROM: A novel localized trapping, 2-bit non-volatile Memory Cell”, IEEE Electron Device Letters vol. 21, n.11 November 2000, describes a so-called NROM memory cell which, with the aid of a cell that can store two bits, enables a cell having an area dimension of 2F2. However, the scalability of such NROM memory cells, which constitute planar components, as also in the case of other conventional EEPROM memories having trapping layers (for example, oxide-nitride-oxide trapping layers or so-called ONO stacks), is limited. For programming the trapping layer, such components utilize, in a known manner, channel hot electrons (CHE) that are injected into the trapping layer from the transistor channel as a result of suitable potential conditions at the source, drain and gate contacts.
The abovementioned scaling problem can be improved by means of memory arrangements having so-called FinFETs, in which the transistor channel is formed in a ridgelike fin made of semiconductor material. It is furthermore advantageous in this case that the read current of the memory element can be set through the height of the fin. Since the gate electrodes in FinFET memory arrangements of this type surround the finlike transistor channel regions from three sides, short channel effects, which restrict scalability, can be effectively suppressed given a suitable choice of the transistor parameters.
FinFET memory arrangements in which the word line run parallel to the fin longitudinal direction (fin direction) have been proposed (cf. DE 102 11 931.7) as particularly advantageous. In the case of very high cell array densities of such semiconductor memories, use has been made of FinFET memory arrangements in which the silicon fins that are spaced apart from one another and arranged parallel to one another are at a distance of less than 50 nm from one another (smallest feature size F less than 50 nm). However, the word lines running between two adjacent fins in the direction of the fin longitudinal axes thereof can easily be short-circuited in the case of such dimensions.
Accordingly, there is a need for a semiconductor memory which enables a high-density cell array without having the above short-circuit problems.
According to one embodiment of the invention, a semiconductor memory comprises: a multiplicity of ridgelike fins made of semiconductor material which are spaced apart from one another and the fin longitudinal directions of which run parallel to one another, a multiplicity of channel regions and conductively doped contact regions being formed in each of the fins and the channel and contact regions being arranged alternately one after the other in the fin longitudinal direction; a multiplicity of word lines which are arranged perpendicular to the fin longitudinal direction, which are parallel to one another and which, as gate electrodes, run over a multiplicity of the channel regions to control the electrical conductivities thereof, the word lines being electrically insulated from the contact and channel regions; a multiplicity of storage layers designed for trapping and outputting charge carriers, at least one of the storage layers being arranged in a manner surrounded by an insulator layer between each of the channel regions and the word line assigned to this channel region; and a multiplicity of bit lines which are arranged obliquely with respect to the word line longitudinal direction and obliquely with respect to the fin longitudinal direction, the bit lines in each case comprising at least one first and one second bit line portion, the longitudinal axes of the first bit line portions running parallel to a first bit line direction and the longitudinal axes of the second bit line portions running parallel to a second bit line direction, the second bit line direction being rotated by an angle that differs from zero degrees relative to the first bit line direction; and each of the bit lines being electrically connected to a multiplicity of the contact regions, there being arranged, between two contact regions of the same fin that are connected to one of the bit lines, a contact region that is not connected to this bit line.
The semiconductor memory according to one embodiment of the invention utilizes so-called FinFETs as “memory transistors”. In this case, the transistor channel is formed in a ridgelike semiconductor fin with doped contact regions adjoining in the fin longitudinal direction. The electrical conductivity of the transistor channel, i.e., of the channel region, can be controlled by means of the field effect via a (control) gate electrode in a known manner. A storage layer is arranged between the gate electrode, which constitutes one of the word lines of the semiconductor memory, and the channel region. The storage layer is electrically isolated from its surroundings, in particular from the channel region and the gate electrode, by means of a thin insulator layer. However, charge carriers, for example, electrons in the case of an n-channel FinFET, given suitable source, drain and gate potentials, can acquire such an energy (hot electrons) that they can overcome the fin insulator layer and be permanently trapped by the storage layer. A charge introduced into the storage layer in this way can be used for storing a “bit” in non-volatile fashion since it influences the characteristic curve, in particular the threshold voltage of the FinFET. These different threshold voltages can be used for the “read-out” of the memory cell. In particular, the read method which is described in the above publication by B. Eitan et al., and which is likewise described in the international patent application WO 99/97000, can be used in this connection. With regard to the programming, reading and erasing method for the semiconductor memory according to embodiments of the invention, reference is thus made to these above publications in their entirety, which are incorporated by reference in their entireties and in this respect form an integral part of the disclosure of the present application.
The problem mentioned in the introduction, namely that, in the case of high-density memory cell arrays, word lines running parallel to the fin longitudinal direction between two adjacent fins can be short-circuited, is solved by embodiments of the invention by virtue of the fact that the word lines are arranged essentially perpendicular to the fin longitudinal direction. At the same time, the bit lines via which the highly doped contact regions (source and drain contacts) of the FinFETs can be contact-connected are arranged obliquely with respect to the fin longitudinal direction and likewise obliquely with respect to the word line direction. There is thus an angle that differs from 0° between the word lines and each of the bit lines. Equally, there is an angle that differs from 0° between the fin longitudinal direction and the longitudinal direction of the bit line.
A further measure according to embodiments of the invention that improves the properties of the semiconductor memory is that each of the bit lines comprises at least two bit line portions. The two bit line portions of each bit line are rotated by an angle with respect to one another in the bit line plane, so that the first bit line direction does not correspond to the second bit line direction. This avoids large length differences between the bit lines which might lead to difficulties during the read-out of the memory cell array on account of different bit line impedances, propagation time effects, etc. If the bit lines comprised a single straight portion arranged obliquely with respect to the word line longitudinal direction and also the fin longitudinal axes, bit lines which electrically connect only a single contact region and bit lines which extend along the entire diagonal of the memory cell array would result in the extreme case.
The two bit line portions may be connected to one another directly above a contact region, so that the “change in direction” of the bit line is effected in the region of the highly doped contact regions. Between these “changes in direction”, the bit line portions extend as straight metal tracks in a bit line plane.
Advantages of the semiconductor memory according to embodiments of the invention include that a read current may be set in a variable manner through variation of the height of the fin, which can be tailored to “high performance” or “low-power” applications. The so-called “double gate” effect of the FinFET arrangement permits potentially better scalability in comparison with planar components, for example, NROM memories. Furthermore, on account of the metallic bit lines, the semiconductor memory according to embodiments of the invention permits faster access times as a result of lower line resistances (shorter RC times when driving parasitic capacitances). The novel arrangement of word and bit lines enables particularly high storage densities even for very small fin spacings of less than 50 nm (F<50 nm).
In one embodiment, each of the bit lines comprises a multiplicity of bit line portions having alternately a first and second bit line direction. The bit lines may have a so-called sawtooth shape, in the case of which the bit lines are arranged in sawtooth-shaped or zigzag-shaped fashion in a bit line plane. In this case, the bit line direction of bit line portions that are connected to one another alternates along the bit line between the first and the second bit line direction.
The bit line portions may have identical lengths. All of the bit lines may be configured as regular sawtooth patterns whose teeth partly intermesh, so that the cell array (apart from possible edge regions) can be completely contact-connected.
In one embodiment, a number Nfins of the fins is provided in each memory sector, and each of the bit line portions is electrically connected to at most Nfins/10 of contact regions of different fins that are adjacent in the bit line direction. Consequently, the bit line portions extend only over a small part of the entire cell array and cross in particular at most a tenth of the fins present in the cell array. In the case of typical cell array sizes of 256×256 word and bit lines, the “amplitude” of the sawtooth pattern is thus less than approximately 25 fins, and in one embodiment, less than 10 fins.
In one particular arrangement, each bit line electrically connects, in sawtooth-shaped fashion, the contact regions that are diagonally adjacent in the cell array. In the case of such a bit line arrangement, a “change in direction” accordingly takes place on each contact region that is electrically connected to the bit line.
The bit lines may have identical area configurations. In particular, the area configurations may be transferred into one another in the bit line plane by means of a parallel displacement along the word line longitudinal direction by a fin period (pitch).
In one embodiment, each of the bit lines is connected to at least Nmin and at most Nmax of the contact regions, so that ((Nmax−Nmin)/Nmax)<20% holds true. The relative deviation in the number of contact regions to which the bit lines are electrically connected thus lies within a range of fluctuation of less than 10%. Consequently, the bit lines have only slightly different numbers of contact regions that are electrically connected to them. This leads to only small variation of electrical characteristic quantities of the bit line, in particular in the impedance thereof, so that evaluation electronics connected to the bit lines may be tuned more simply. Ideally, all of the bit lines have an essentially identical number of contact regions connected to them, so that the bit lines have the same “electrical length”.
In one embodiment, the fin width is equal to the word line width and equal to the perpendicular distance between adjacent word lines. The fin width, i.e., the perpendicular distance between the opposite fin side areas running parallel, is chosen to be equal to the word line width and the word line spacing, thus resulting in a square 1:1 cell array grid. Such a cell array arrangement enables the highest storage density.
In one embodiment, two bit line planes are provided, and bit lines that are adjacent in the word line longitudinal direction are arranged in different bit line planes. Such an embodiment is of interest particularly when, as described above, the fin width, bit line width, word line width and the word line spacing correspond to the minimum feature size F of the semiconductor memory. In such a case, a sawtooth-shaped bit line leads to distances between adjacent bit lines which would be smaller than the minimum feature size F. This problem can be solved by arranging respectively adjacent bit lines in different bit line planes, i.e., in different metal planes. By way of example, the odd bit lines are provided in a first bit line plane, and the even bit lines are provided in a second bit line plane (located at a higher level) that is further away from the semiconductor substrate. The higher bit line plane is connected by means of deep contact holes to the contact regions of the FinFETs that are to be connected. A 4F2 memory cell that can store two bits can be obtained with a bit line arrangement of this type. The programming and read concept known from NROM memories is used in this case.
In one embodiment, the bit line directions are rotated by an angle of approximately 45 degrees relative to the word line and fin longitudinal directions and the angle between the first and the second bit line direction is 90°. Such an arrangement is advantageous particularly in the case of a memory cell array having a square 1:1 arrangement of the cells and permits a symmetrical configuration of the bit lines.
The storage layers are trapping layers and the insulator layers are oxide layers. The trapping layer may be a nitride layer, in particular a silicon nitride layer, which is surrounded by oxide layers, in particular silicon dioxide layers. Such an oxide-nitride-oxide arrangement between the (control) gate electrode and the channel region is referred to as an ONO stack. However, it is also possible to use other trapping materials, for example, so-called “silicon-rich oxide” or else undoped polysilicon or other high-k materials. Such trapping layers have a large density of defect states (so-called “trap states”) which are suitable for trapping and emitting charge carriers (electrons or holes).
The invention thus provides a non-volatile semiconductor memory in a “virtual ground” arrangement (VGA) with a cell array density of 2F2 per bit, in the case of which the bit lines lie in sawtooth-shaped fashion and alternately in the first and second metal planes (bit line planes). This results in a memory arrangement having the storage density of planar NROMs, with the advantage of an adjustable read current, the “double gate” effect by virtue of the FinFET arrangement and thus, a potentially better scalability and also a faster access time to each memory cell by virtue of the metallic bit lines. The very high storage density of 2F2 per bit may also be achieved for fins that are very close together where F<50 nm.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
The cross-sectional view illustrated in
Hot electrons generated in the transistor channel as a result of suitable potential conditions can overcome the oxide layer 18 and penetrate into the storage layer 14 as so-called “channel hot electrons” (CHE). Their presence in the storage layer 14 brings about, in a known manner, a shift in the threshold voltage of the FinFET, as a result of which a “bit” can be programmed. The scalability of the FinFET is improved compared with planar components on account of the “double gate” effect of the word line WL on the channel region, in particular from the fin side areas 12. To produce such FinFET arrangements, SOI substrates (silicon on insulator) are suitable, in particular, in the case of which the ridgelike fins made of semiconductor material, e.g., silicon, are arranged on a buried oxide layer BOX which, for its part, is applied on a silicon substrate. The fins FIN are formed in the top silicon layer (body silicon layer).
The width of the fins FIN illustrated in
Whereas in the case of the FinFET arrangement illustrated in
The ridgelike fins made of semiconductor material FIN1, FIN2 run from top to bottom in the plane of the drawing. The fin longitudinal direction is illustrated by the direction arrow designated by (FIN). In the embodiment illustrated in
The word lines WL1, WL2 run perpendicular to the fin longitudinal direction (FIN). The direction of the word lines is illustrated by the direction arrow designated by (WL). The word lines WL1, WL2 form the (control) gate electrodes of the FinFETs and run over the channel regions of the fins FIN1, FIN2. Each word line WL1, WL2 has precisely one crossover point with each fin FIN1, FIN2. In the case of the embodiment illustrated in
The bit lines BL1, BL2 are comprised of a multiplicity of bit line portions 22, 24 connected to one another. The first bit line portion 22 runs in a first bit line direction (BL1) while the second bit line portion 24 runs along a second bit line direction (BL2). The bit line directions (BL1), (BL2) run obliquely with respect to the word line longitudinal direction (WL) and the fin longitudinal direction (FIN). In the case of the embodiment illustrated in
The bit lines BL1, BL2 run over the contact regions S/D formed in the fins FIN1, FIN2. The metallic bit lines BL are electrically connected to the underlying contact regions S/D through contact holes. In the case of the embodiment illustrated in
Although the sawtooth-shaped bit line course depicted in
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
| Number | Date | Country | Kind |
|---|---|---|---|
| DE 102 41 171.9 | Sep 2002 | DE | national |
This application is a continuation of co-pending PCT patent application No. PCT/EP03/09294, filed 21 Aug. 2003, which claims the benefit of German patent application serial number DE 102 41 171.9, filed 5 Sep. 2002. Each of the aforementioned related patent applications is herein incorporated by reference in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/EP03/09294 | Aug 2003 | US |
| Child | 11074345 | Mar 2005 | US |
