The disclosed system and method relate to semiconductor memories. More specifically, the disclosed system and method relate to word line layouts for semiconductor memories.
Static random access memories (“SRAM”) include a plurality of cells disposed in rows and columns to form an array. SRAM cells include a plurality of transistors coupled to bit lines and word lines that are used to read and write a bit of data to the memory cell. Dual port SRAMs are a specific type of SRAM that enables multiple reads or writes to occur at approximately the same time. Conventional dual port SRAM structures include word lines in different metal layers, which causes different capacitive loading due to the different metal layers being used to route signals of the SRAM. Such different capacitive loading results in a disparity between operating times of the word lines, which affects the speed of the overall SRAM.
The disclosed layout advantageously provides for a symmetric resistance and capacitive (“RC”) loading across the word lines (“WL”) of a semiconductor memory. The symmetric loading enables semiconductor memory to operate at a faster speed than conventional semiconductor memories with uneven RC loading.
As best seen in
Bit cell 102 also includes a plurality of pass transistors 126, 128, 130, and 132. In some embodiments, transistors 126, 128, 130, and 132 are NMOS transistors, although one skilled in the art will understand that transistors 126, 128, 130, and 132 may be implemented as PMOS transistors. Transistor 126 has its gate coupled to word line A_WL at node 134, its source coupled to node 116, and its drain coupled to bit line A_BL at node 136. Transistor 128 has its gate coupled to word line B_WL at node 138, its source coupled to node 116, and its drain coupled to bit line B_BL at node 140. Transistor 130 has its source coupled to node 120, its drain coupled to bit line A_BLB at node 142, and its gate coupled to word line A_WL at node 144. Transistor 132 has its source coupled node 120, its drain coupled to bit line B_BLB at node 146, and its gate coupled to word line B_WL at node 148.
As shown in
Bit lines A_BLB and B_BLB are shielded from one another by voltage supply lines for VSS. As will be understood by one skilled in the art, the sources of one or more pull-down transistors 118-1 and 124-1 may be coupled to VSS by a via that is not shown in
Bit cell 102-2 has a different layout than the layout of bit cell 102-1. For example, the left-most side of bit cell 102-2 (and the right-most side of bit cell 102-1) includes a via for nodes 148-1 and 134-2 at which the respective gates of transistor 132-1 and transistor 128-2 are coupled to word line B_WL. The via for nodes 148-1 and 134-2 is disposed between bit lines B_BLB of column 106-1 and A_BL of column 106-2. A power supply line for VSS extends parallel to bit line A_BL and shields bit line B_BL from bit line A_BL, which extends adjacent to another power supply line for VSS. Vias for connecting one or more of pull-down transistors 118-2 and 124-2 to VSS are not shown in
Node 138-2, which couples the gate of transistor 128-2 to bit line B_BL, is disposed between the power supply lines for VSS that shield bit lines A_BL and B_BL. The via that couples node 138-2 to word line B_WL also serves as node 148-1 to connect transistor 132-1 to word line B_WL. Bit line B_BL is shielded from bit line B_BLB by a power supply line for VDD. The vias that couple the gates of pull-up transistors 110-2 and 112-2 to word line A_WL are not shown in
In this embodiment, word lines A_WL and B_WL of row 104 have approximately equal load. For example, the bit cell 102-1 includes three vias coupled to word line A_WL and one via coupled to word line B_WL, and bit cell 102-1 includes one via coupled to word line A_WL and three vias coupled to word line B_WL. Accordingly, word line A_WL and word line B_WL of row 104 are each coupled to four vias and approximately equal capacitive and resistive loading. As will be understood by one skilled in the art, an approximately equal load includes loads that differ by five percent.
The manner in which the load on a pair of word lines in a particular row is equalized may be varied. For example,
In some embodiments, the bit cells are arranged in a row to provide approximately equal resistive and capacitive (“RC”) loading, but are not arranged in an alternating manner. For example,
In some embodiments, a semiconductor memory includes first and second word lines. A first bit cell of a first type is coupled to a first one of a plurality of bit lines and has a first layout in which the first bit cell of the first type is coupled to the first word line with a first number of vias and to the second word line with a second number of vias. A first bit cell of a second type is coupled to a second one of the plurality of bit lines and has a second layout in which the first bit cell of the second type is coupled to the first word line with a third number of vias and to the second word line with a fourth number of vias. A load on the first word line is approximately equal to a load on the second word line.
In some embodiments, a semiconductor memory includes a plurality of bit lines extending in a first direction, a word line driver circuit, and first and second word lines. The first word line extends in a second direction and is coupled to the word line driver circuit. The second word line extends in the second direction and is coupled to the word line driver circuit. A first bit cell of a first type is coupled to a first one of the plurality of bit lines and has a first layout in which the first bit cell of the first type is coupled to the first word line with a first number of vias and to the second word line with a second number of vias. A first bit cell of a second type is coupled to a second one of the plurality of bit lines and has a second layout in which the first bit cell of the second type is coupled to the first word line with a third number of vias and to the second word line with a fourth number of vias. A load on the word line driver circuit from the first word line is approximately equal to a load on the second word line circuit from the second word line.
Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the invention, which may be made by those skilled in the art without departing from the scope and range of equivalents of the invention.
Number | Name | Date | Kind |
---|---|---|---|
5955768 | Liaw et al. | Sep 1999 | A |
5973985 | Ferrant | Oct 1999 | A |
6370078 | Wik et al. | Apr 2002 | B1 |
6498758 | Pomar et al. | Dec 2002 | B1 |
6665204 | Takeda | Dec 2003 | B2 |
6756652 | Yano et al. | Jun 2004 | B2 |
6822300 | Nii | Nov 2004 | B2 |
7023056 | Liaw | Apr 2006 | B2 |
7319602 | Srinivasan et al. | Jan 2008 | B1 |
7405994 | Liaw | Jul 2008 | B2 |
20010043487 | Nii et al. | Nov 2001 | A1 |
20030048256 | Salmon | Mar 2003 | A1 |
20040120209 | Lee et al. | Jun 2004 | A1 |
20050047256 | Yang | Mar 2005 | A1 |
20060028860 | Lien et al. | Feb 2006 | A1 |
Entry |
---|
Nii, K. et al., “A 90 nm Dual-Port SRAM with 2.04 um2 8T-Thin Cell Using Dynamically-Controlled Column Bias Scheme”, IEEE International Solid-State Circuits Conference, Session 27, 2004, pp. 27.9. |
Wolf, S. Ph.D., “Silicon Processing for the VLSI Era”, Process Integration, 1990, (2):160-161. |
“Renesas Technology Develops 90 nm Dual-Port SRAM for SoC”, DStar, printed on Apr. 6, 2005, 3 pages, World Wide Web, http://www.hpcwire.com/dsstar/04/0224/107497. |