Zero-flag generator for adder

Abstract

Parallel processing architecture is used for an adder and its "look-ahead" zero-flag generator, which generates a flag signal for the most significant bit of the sum of the adder. The look-ahead zero-flag is generated with combinatorial logic circuits, which are fed from the addends and augents of the different bits for the adder and then decoded. The combinatorial logic circuits may comprise AND gates and XOR gates in a gate-array, and the decoder may be a programmable logic array (PLA). The computation time for the zero-flag thus generated is shorter than the computation time for the sum of the adder.

Description

BACKGROUND

This invention is related to adders for the arithmatic logic unit (ALU) of a computer.

An adder is an important element in an arithmatic logic unit (ALU). Two n-bit input data and carry data can produce (n+1) bit sum output. In an ALU, the adder is often accompanied with a "zero-flag" generator to determine whether the sum output of the most significant bit is zero or not for activating other related control circuits. A conventional zero-flag generator, as shown in FIG. 1, is composed of a group of NOR logic gates. As shown in this figure, the data inputs Din.sub.-- a and Din.sub.-- b are summed with the carry signal CIN of a previous stage in an adder. For the (n-1)th bit, the sum output cannot be determined until the output of the least significant bit is rippled through all the intermediate bits to reach the (n-1)th bit. The adder has a sum output OVF and a carry output Co, which are fed to the terminals WE.sub.-- v and WE.sub.-- c respectively. Besides, another output is fed to a zero-flag generator A=0? to determine whether the sum is zero or not. If the sum is zero, a zero-flag signal appears on line Z and is fed to terminal WE.sub.-- Z.

In this process, the zero-flag signal is generated after an adder has produced a result, and is not predicted ahead of time. Thus, the processing speed is slow without the "zero look ahead" feature. Only one relative solution to this problem is disclosed in the U.S. Pat. No. 4,878,189. In this patent, the arithmatic logic unit (ALU) is executed for addition function. The patented circuit belongs to traditional implementation methods, in that there is delay of the critical path in the design of the central processing unit (CPU).

SUMMARY

An object of this invention is to implement a "look-ahead" zero-flag generator in parallel with the adder in an ALU, so that addition and zero-flag detection are processed simultaneously to speed up the operation. Another object of this invention is to obtain a zero-flag signal before the summation signal of an adder. Still another object of this invention is to use Exclusive OR gates and AND gates to implement the "look-ahead" zero-flag generator. A further object of this invention is to utilize a programmable logic array (PLA) to decode the large number of conditions for realizing the algorithms of the zero-flag generator.

The object is achieved in this invention by processing signals to the zero-flag generator in parallel with processing signals to the adder for achieving the zero look-ahead function. The preprocessing utilizes AND and Exclusive-OR gates to define all the combinations for yielding a zero-flag for the most significant bit of the sum of the adder. The large number of conditions can be implemented with a gate-array and decoded with a programmable logic array to yield the zero-flag signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a conventional architecture of a zero-flag generator.

FIG. 2 shows the block diagram of the zero-flag generator based on the present invention.

FIG. 3 shows the schematic entry in GENESIL enviroment as a practical example of the present invention.

FIG. 4 shows the layout of the example shown in FIG. 3.

FIG. 5 (Table 1) shows the delay time of a conventional zero-flag generator (16.7 ns), as computed by two computer analysis programs--TA and SPICE.

FIG. 6 (Table 2) shows the delay time (12.8 ns) of a zero-flag generator of the present invention, as computed by the computer analysis programs--TA and SPICE.

FIG. 7 (Table 3) shows the source code equations of the PLA used in the example shown in FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The block diagram of the present invention is shown in FIG. 2. There are n number of XOR gates and n number of AND gates in the form of a gate array, where n is the maximum number of bits of the addend or the augent. The gate array is used to produce the XOR.sub.i and AND.sub.i (i=0,1,2, . . . ,n-1) signals for a PLA. The decoded PLA output serves as a zero detect bit.

The necessary PLA source code equations can be deduced as follows:

Let A.sub.n =<a.sub.n-1, a.sub.n-2, . . . ,a.sub.o > be the augent, where a.sub.n-1 is the most significant bit (MSB), and a.sub.o is the least significant bit (LSB). B.sub.n =<b.sub.n-1, b.sub.n-2, . . . ,b.sub.o > be the addend, where b.sub.n-1 is the MSB, and b.sub.o is the LSB. CIN=<C.sub.-1 > be the LSB carry bit. S.sub.n =<S.sub.n-1, S.sub.n-2, . . . ,S.sub.o >=A.sub.n 30 B.sub.n +CIN is the total sum of the n-th bit, where S.sub.n-1 is the MSB, and S.sub.o is the LSB.

Define XOR.sub.i =a.sub.i b.sub.i, AND.sub.i =a.sub.i .multidot.b.sub.i (i=0,1, . . . ,n-1). The value of S.sub.n can be zero. The conditions for the S.sub.n =0 or zero detect bit to be "1" are as follows:

case 1: XOR.sub.i =1(i=0,1, . . . ,n-1), AND.sub.i =0 (i=0,1, . . . ,n-1), CIN=1.

(*This condition can be seen quite readily. If the AND gate output for every bit is "0", and the XOR gate output for every bit is "1", then a.sub.i or b.sub.i is "1", but not both (for i=0,1, . . . ,n-1). Thus, when CIN=1 is summed with a.sub.o and b.sub.o, a sum S.sub.o =0 and a carry signal c.sub.o =1 are produced. In this manner, the sum S.sub.o and the carry signal "1" are propagated toward the (n-1)th bit. The sum S.sub.o must then be "0".

case 2: XOR.sub.i =1 (i=1,2, . . . ,n-1), AND.sub.i =1 (i=0), CIN=0, XOR.sub.i =0 (i=0), AND.sub.i =0 (i=1,2, . . . ,n-1).

(*Since AND.sub.0 =1 and XOR.sub.i =0, that means that a.sub.o =b.sub.0 =1 and carry signal c.sub.o 32 1. For all the higher significant bits (i.e. i>0), XOR.sub.i =1 means that either a.sub.i or b.sub.i is "1" but not both. Thus, when C.sub.0 =1 is summed with a.sub.1 and b.sub.1, a sum S.sub.1 =0 and a carry signal C.sub.1 =1 is produced. In this manner, the sum S.sub.1 and the carry signal "1" are propagated toward the (n-1)th bit. The sum S.sub.n must then be "0". With similar reasoning, the following conditions can be deduced)

case 3: XOR.sub.i =1 (i=2,3, . . . ,n-1), AND.sub.i =1 (i=1), CIN=0, XOR.sub.i =0 (i=0,1), AND.sub.i =0 (i=0,2,3, . . . ,n-1). case 4: XOR.sub.i =1 (i=3,4, . . . ,n-1), AND.sub.i =1 (i=2), CIN=0, XOR.sub.i =0 (i=0,1,2,), AND.sub.i =0 (i=0,1,3, . . . ,n-1). case n: XOR.sub.1 =1 (i=n-1), AND.sub.i =1 (i=n-2), CIN=0. XOR.sub.i =0 (i=0,1, . . . ,n-2), AND.sub.i =0 (i=0,1, . . . ,n-3,n-1) case n+1: XOR.sub.i =0 (i=0,1, . . . ,n-1), AND.sub.i =1 (i=n-1), CIN=0. case n+2; XOR.sub.i =0 (i=0,1, . . . ,n-1), AND.sub.i =0 (i=0,1, . . . ,n-1), CIN=0. The foregoing equations can also be proved by the associative law of Boolean algebra.

The foregoing Boolean conditions can be implemented by the architecture shown in FIG. 2. The XOR gates and the AND gates for n number of bits are implemented in the Gate-Array block, which have n outputs of XOR.sub.i and n outputs of AND.sub.i. These XOR gate and AND gate outputs are decoded by a PLA. As a PLA has an AND plane and an OR plane, the different XOR.sub.i and AND.sub.i outputs from the gate array are fed as inputs to the AND plane and perform the AND function for each case. Each condition produces a "1" zero detect bit output. The outputs from the AND plane are then fed to the OR plane to produce the zero-flag signal.

The present method has been used in a developmental work station, SPARC, as a practical example. The zero-flag generator is designed into the integer unit (IU), (i.e., SPARC CPU) to improve the speed of the control circuit. FIG. 3 shows the schematic entry, which is a representation diagram of logic circuit connected by icons of logic function, in a CAD tool GENESIL enviroment. This CAD tool is from the Mentor Graphics Co. for IC design. The carry look ahead adder based on the present invention uses a custom layout. The gate-array uses a standard cell approach. The PLA also uses custom layout, which are based on the source code equations described earlier. A 1.2 micron design rule is used in the layout. The circuit was analyzed with the TA timing analysis program and the SPICE circuit analysis program. The delay time for the worst-case critical path is 12.8 ns (see Table 2) for the present invention, as compared to the delay time of 16.7 for conventional circuit.

If the gate-array is implemented with custom layout, the chip area can be reduced. The circuits used in the gate array can also share with certain "look-ahead carry" circuits used in the adders, because a gate array has the same logic function definition in some adder structure, (e.g. carry look ahead adder). In such a case, the gate-array may not be needed.

While the foregoing description is based on addition, the same technique can be used for subtraction to obtain a zero-flag, by changing the input to its 1's or 2's complement. The technique falls within the scope of this invention.

Claims

1. A zero-flag generator for digital adder with n-bits of input data including a one-bit input carry signal for producing output sum signal and an output carry signal comprising:

means for detecting said output sum no later than the production of said sum from said adder, comprising:

a plurality of logic combinations of only Exclusive-OR (XOR) gates and AND gates: having individual inputs for each of said bits which are the same as the individual inputs for the corresponding bits of said adder for outputting the logic combination signals XORi and ANDi, where i=0,1, . . . ,n-1, for each of said bits, and

a decoder for decoding the outputs of said logic gate combinations with an carry to generate a zero-flag in accordance to the number of combinations of said input carry and said logic combination signals for said zero-flag to be zero.

2. A zero-flag generator as described in claim 1, where each of said logic gate combinations comprises only an XOR gate and an AND gate.

3. A zero-flag generator as described in claim 2, wherein logic gate combinations are implemented with gate arrays.

4. A zero-flag generator as described in claim 2, wherein said decoder decoding outputs of said logic gate combinations is a programmable logic array (PLA).

5. A zero-flag generator as described in claim 2, wherein said conditions for said zero-flag to be zero with addends a.sub.i and augends b.sub.i (where i=0,1,2, . . . ,n-1) and the carry signal to the least significant bit CIN are:

case 1: XOR.sub.i =1 (i=0.1, . . . ,n-1), AND.sub.i =0 (i=0,1, . . . ,n-1),CIN=1;

case 2: XOR.sub.i =1 (i=1,2, . . . ,n-1), AND.sub.i =1 (i=0), CIN=0, XOR.sub.i =0, (i=0), AND.sub.i =0 (i=1,2, . . . ,n-1);

case 3: XOR.sub.i =1 (i=2,3, . . . ,n-1), AND.sub.i =1 (i=1), CIN=0, XOR.sub.i =0 (i=0,1), AND.sub.i =0 (i=0,2,3, . . . ,n-1);

case 4: XOR.sub.i =1 (i=3,4, . . . ,n-1), AND.sub.i =1 (i=2), CIN=0, XOR.sub.i =0 (i=0,1,2), AND.sub.i =0 (i=0,1,3, . . . ,n-1);

case n: XOR.sub.i =1 (i=n-1), AND.sub.i =1 (i=n-2), CIN=0, XOR.sub.i =0 (i=0,1, . . . ,n-2), AND.sub.i =0 (i0,1, . . . ,n-3,n-1);

case n+1: XOR.sub.i =0 (i=0,1, . . . ,n-1), AND.sub.i =1 (i=n-1), CIN=0; . . .

case n+2: XOR.sub.i =0 (i=0,1, . . . ,n-1), AND.sub.i =0 (i=0,1, . . . ,n-1), CIN=0.

6. A zero-flag generator as described in claim 5, wherein said different in claim 6 are decoded with a PLA using the different conditions for zero-flag of said XOR gates and said AND gates in each case as inputs to the AND planes of said PLA and output of the OR plane of said PLA as said zero-flag signal.