Patent Application
20240339467
Many modern-day electronic devices contain digital image sensors. Digital image sensors may be backside illumination sensors or frontside illumination sensors. Digital image sensors may utilize multi-chip packaging to lower the area per pixel and increase the resolution of the resulting device.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
An image sensor may comprise a pixel array having a plurality of pixels arranged in rows and columns. The pixels comprise individual photodetectors in a substrate of a first IC chip. The pixels further comprise individual transfer transistors coupling the individual photodetectors to individual floating diffusion nodes in the substrate. The floating diffusion nodes may be electrically coupled to an interconnect structure of a second IC chip through a metal-metal (M-M) and dielectric-dielectric (D-D) bonding layer. The M-M and D-D bonding layer comprises a plurality of conductive pads surrounded by a dielectric material.
The second IC chip accommodates a plurality of transistors individual to the pixels. These transistors include a plurality of source-follower transistors, a plurality of reset transistors, and a plurality of selection transistors which are configured to read the photodetectors and selectively pass the readings of the photodetectors to an application specific integrated circuit (ASIC) on a third IC chip. Arranging the transistors at the second IC chip, rather than at the first IC chip, frees space on the first IC chip to allow shrinking of the pixels without reducing the size of the photodetectors. This, in turn, increases a maximum resolution of the image sensor. A higher maximum resolution is desirable as it increases a quality of an acquired image.
During operation of the image sensor, charges are transferred from the individual photodetectors to gates of the plurality of source-follower transistors through the conductive pads within the M-M and D-D bonding layer. Due to a proximity of the conductive pads with respect to one another, there may be a mutual inductance and mutual capacitance between the conductive pads. The mutual inductance and capacitance between the conductive pads results in cross-talk between the conductive pads. The resulting cross-talk increases as the image sensor is scaled down and reduces an accuracy of a captured image. The cross-talk can be avoided by completely surrounding the conductive pads with electrically grounded shield lines. However, completely surrounding each conductive pad with a shield line increases a pattern density of the M-M and D-D bonding layer, leading to a higher rate of patterning failure, increased dishing, and a lower bond interface quality between the first IC chip and the second IC chip.
The present disclosure relates to an image sensor integrated chip (IC) comprising a plurality of pixel blocks arranged in an array in rows and columns. A plurality of conductive pads are arranged within the plurality of pixel blocks. A corrugated shield line extends between conductive pads within a row of pixel blocks, but does not extend between the conductive pads in the row and additional conductive pads in different rows of pixel blocks. The corrugated shield line is configured to interrupt electromagnetic fields and reduce the mutual inductance and capacitance between neighboring ones of the conductive pads in the row of pixel blocks. The reduction in mutual inductance reduces an amount of interference, resulting in the image sensor IC producing a higher quality image. Because the pixel blocks may be read on a row-by-row basis, the lack of a shielding line between the conductive pads and the additional conductive pads will not significantly impact cross-talk between different rows of pixel blocks. However, not putting shield lines between the conductive pads and the additional conductive pads results in a reduced pattern density of the M-M and D-D bonding layer, thereby reducing an amount of patterning failures and enhancing a bond interface quality between a first IC chip and a second IC chip.
As shown cross-sectional view 100a, the IC device comprises a first IC chip 101 with a first M-M and D-D bonding layer 106 and a second IC chip 103 with a second M-M and D-D bonding layer 115. The first M-M and D-D bonding layer 106 comprises a first plurality of conductive pads 102 that are electrically coupled to a first wire level 110a by a first plurality of bond contacts 112a. The second M-M and D-D bonding layer 115 comprises a second plurality of conductive pads 114 that are electrically coupled to a second wire level 110b by a second plurality of bond contacts 112b. Further, the first plurality of conductive pads 102 are electrically coupled to the second wire level 110b by the second plurality of bond contacts 112b and the second plurality of conductive pads 114 in the second M-M and D-D bonding layer 115.
The first plurality of conductive pads 102 are surrounded by a first dielectric layer 108a, and the second plurality of conductive pads 114 are surrounded by the second dielectric layer 108b. The first and second dielectric layers 108a, 108b are bonded to each other at a first bond interface 105. In some embodiments, the second plurality of conductive pads 114 are in the second IC chip 103 and are bonded to the first plurality of conductive pads 102 at the first bond interface 105. As such, the first bond interface 105 has a dielectric-to-dielectric bond interface and a metal-to-metal bond interface and is hence a hybrid or mix of the two bond interfaces. The symmetrical bonding of the first plurality of conductive pads 102 to the second plurality of conductive pads 114 results in a stronger bond between the first IC chip 101 and the second IC chip 103, as the first plurality of conductive pads 102 bond more effectively to the second plurality of conductive pads 114 than a second dielectric layer 108b of the second IC chip 103.
In some embodiments, the first plurality of bond contacts 112a, the second plurality of bond contacts 112b, the first plurality of conductive pads 102, the second plurality of conductive pads 114 or any combination of the foregoing are or comprise a metal such as copper (e.g., Cu), aluminum, silver (e.g., Ag), gold (e.g., Au), and/or the like. In some embodiments, the first and second dielectric layers 108a, 108b respectively comprise one or more separate dielectric materials. The first dielectric layer 108a is bonded to the second dielectric layer 108b through van der Waals forces. In some embodiments, the first dielectric layer 108a and the second dielectric layer 108b may be or comprise one of silicon oxide (e.g., SiO2), silicon nitride (e.g., Si3N4), silicon oxynitride, and/or the like.
As shown in cross-sectional view 100a and top layout view 100b, the integrated chip comprises a plurality of pixel blocks 118 respectively comprising one or more photodetectors. For example, a pixel block of the plurality of pixel blocks 118 may comprise 4 photodetectors (e.g., arranged in a 2×2 array), 8 photodetectors (e.g., arranged in a 2×4 array), or other similar values. The plurality of pixel blocks 118 are arranged in rows extending in a first direction 122 and columns extending in a second direction 124 perpendicular to the first direction 122. The plurality of pixel blocks 118 respectively comprise one of the first plurality of conductive pads 102. During a read operation, the first plurality of conductive pads 102 transfer charges from individual photodetectors within the plurality of pixel blocks 118 to gates of source-follower transistors (e.g., within second IC chip 103) on a row-by-row basis. For example, during a read operation signals may be transferred from pixel blocks within a first row 120a while pixel blocks in a second row 120b are set to a high voltage (e.g., VDD), and then signals may be subsequently transferred from pixel blocks within the second row 120b while pixel blocks in the first row 120a are set to a high voltage. Because the read operation is performed on a row-by-row basis, minimal noise is generated between conductive pads in neighboring rows (e.g., between conductive pads in the first row 120a and the second row 120b) during the read operation.
A first corrugated shield line 104 extends in a zig-zag pattern that laterally separates neighboring ones of the first plurality of conductive pads 102 within the row of the plurality of pixel blocks 118. For example, a first conductive pad within the first row 120a is laterally spaced from the second conductive pad within the first row 120a by the first corrugated shield line 104. The first corrugated shield line 104 has outermost surfaces that weave around neighboring ones of the first plurality of conductive pads 102 within the row. Outermost edges of the first corrugated shield line 104 are located at a top and a bottom of the zig-zag pattern, as viewed in top layout view 100b. In some embodiments, an entirety of the first corrugated shield line 104 is within a corresponding row of the plurality of pixel blocks 118. For example, the first corrugated shield line 104 may have outermost edges (e.g., topmost and bottommost edges as viewed in top layout view 100b) that are set-back from outermost edges (e.g., topmost and bottommost edges as viewed in top layout view 100b) of the first row 120a by non-zero distances. In some embodiments, an entirety of the first corrugated shield line 104 within a row is confined between opposing outermost edges (e.g., between top and bottom edges as viewed in top layout view 100b) of a plurality of conductive pads within the row. In some embodiments, a first corrugated shield line 104 within a row is outside of a neighboring row (e.g., does not extend from within the row to within the neighboring row). In some embodiments, the first corrugated shield line 104 is or comprises a metal such as copper (e.g., Cu), silver (e.g., Ag), gold (e.g., Au), aluminum and/or the like.
In some embodiments, the first corrugated shield line 104 may comprise shield line segments 104b-104c and one or more shield nodes 104a having a greater width than the shield line segments 104b-104c. In some embodiments, the one or more shield nodes 104a may have a same top geometry (e.g., a square shaped geometry) as a top geometry of the first plurality of conductive pads 102. In some such embodiments, the first plurality of conductive pads 102 are interleaved with shield nodes 104a in an array, such that placement of first plurality of conductive pads 102 and the shield nodes 104a alternate over both rows and columns. The first plurality of conductive pads 102 have a zig-zag layout along rows and columns. Additionally, a plurality of shield line segments 104b-104c extend in a zig-zag layout along rows and columns, and between neighboring shield nodes 104a. In some embodiments, a second corrugated shield line 116 is in the second IC chip 103 and is bonded to the first corrugated shield line 104 over a length of the first corrugated shield line 104. Further, a shield node of the second corrugated shield line 116 is directly between a first and a second one of the second plurality of conductive pads 114. In some embodiments, the second corrugated shield line 116 may comprise shield line segments and one or more shield nodes having a greater width than the shield line segments.
The first corrugated shield line 104 is biased in a manner that is configured to mitigate cross-talk between neighboring ones of the first plurality of conductive pads 102 within a row (e.g., first row 120a or second row 120b) of the plurality of pixel blocks 118. In some embodiments, to avoid coupling between neighboring conductive pads the first corrugated shield line 104 may be electrically grounded, electrically biased, or electrically floating. Because the first plurality of conductive pads 102 within a row are laterally separated by the first corrugated shield line 104, mutual inductance and capacitance between the first plurality of conductive pads within the row are reduced. This results in charges transferred through a first one of the first plurality of conductive pads having a diminished effect on other ones of the first plurality of conductive pads and vice versa. As a result, interference caused by a proximity of the first plurality of conductive pads to one another is reduced, and a pixel array split amongst the first IC chip 101 and the second IC chip 103 may output a higher quality image than would otherwise be possible. Furthermore, because the plurality of pixel blocks 118 are read on a row-by-row basis, a corrugated shield line is not needed between neighboring rows to provide noise mitigation, and thus can be avoided thereby limiting M-M and D-D bonding layer pattern density and resulting in a high-quality bonding interface.
As shown in the cross-sectional view 200a of
During the bonding process, bubbles of gas may be trapped between the first dielectric layer 108a and the second dielectric layer 108b. The first plurality of corrugated shield lines 104 may help to discharge the gas that may be trapped between the first and second dielectric layers 108a, 108b due to having different surface conditions at the time of bonding, due to dishing, or other effects. The first plurality of corrugated shield lines 104 may provide a path for the gas to escape the bubbles that would otherwise form between the first and second dielectric layers 108a, 108b.
In some embodiments, such as those shown in
As shown in the cross-sectional view 200b of
The third plurality of conductive pads 204 are directly and respectively beneath the first plurality of conductive pads 102. The third plurality of conductive pads 204 are bonded respectively to the second plurality of bond contacts 112b at the first bond interface 105. The first corrugated shield line 104 is spaced from the first bond interface 105 by a third dielectric layer 108c in the third M-M and D-D bonding layer 203. In some embodiments, a bottom surface of the first corrugated shield line 104 is level with a top surface of the third M-M and D-D bonding layer 203.
The third dielectric layer 108c bonds more effectively to the second dielectric layer 108b than the first corrugated shield line 104. Therefore, because the third M-M and D-D bonding layer 203 spaces the first plurality of corrugated shield lines 104 from the first bond interface 105, a better bonding between the first IC chip 101 and the second IC chip 103 results.
As shown in the cross-sectional view 200c of
As shown in the top layout view 300a of
Eight photodetectors are in a pixel block comprising a pixel. The eight photodetectors overlie and are coupled to one conductive pad and further overlie one shield node. For example, a first pixel 304 (comprising a first plurality of photodetectors) overlies and is coupled to a first conductive pad 102a and further overlies a shield node 104a. The eight photodetectors are coupled to the first conductive pad 102a through two floating diffusion nodes (not shown) respectively positioned directly over the first conductive pad 102a and the shield node 104a. Additional pixels 306, 308 are in a first row 310 with the first pixel 304. For example, a second pixel 306 (comprising a second plurality of photodetectors) are directly over and electrically coupled to a third conductive pad 102c. In some embodiments, the first plurality of photodetectors and the second plurality of photodetectors border one another. The first plurality of conductive pads 102 in the first row 310 are offset from one another in a zig-zag line 309 beneath the pixels 304, 306, 308.
In some embodiments, a first shield line segment 104b of the first corrugated shield line 104 is substantially normal to a part of the zig-zag line 309 extending from the first conductive pad 102a to a third conductive pad 102c, and a second shield line segment 104c of the first corrugated shield line 104 is substantially parallel to the part of the zig-zag line 309 extending from the first conductive pad 102a to the third conductive pad 102c. The first shield line segment 104b and the second shield line segment 104c are coupled to a shield node 104a that is equidistant from the first conductive pad 102a and the second conductive pad 102b, and wherein the shield node 104a is offset from the first conductive pad 102a in a first direction and offset from the second conductive pad in a second direction normal to the first direction. A part of the zig-zag line 309 extending between the third conductive pad 102c and a second conductive pad 102b is at a 45-degree angle from a line 318 extending between the second conductive pad 102b and the first conductive pad 102a. The line 318 extending between the first conductive pad 102a and the second conductive pad 102b extends through the shield node 104a.
In some embodiments, a second pixel 306 of the additional pixels 306, 308 overlies and is coupled to a third conductive pad 102c and further overlies an additional shield node 104a proximate to the first conductive pad 102a and connected to the shield node 104a under the first pixel 304 by the first shield line segment 104b. In further embodiments, the first pixel 304 and the second pixel 306 repeat periodically and alternatingly along an axis extending parallel to the first row 310 and a second row 312 and wherein shield nodes 104a of the repeated first and second pixels 304, 306 are electrically coupled by repeated first and second shield line segments 104b, 104c of the first corrugated shield line 104. In some embodiments, the first and second rows 310, 312 repeat periodically and alternatingly along a second axis extending perpendicular to the first and second rows 310, 312, and the first corrugated shield line 104 repeats periodically in the repeated first and second rows 310, 312.
During operation, the pixels 304, 306, 308 in the first row 310 are read in parallel, with the photodetectors in the pixels 304, 306, 308 being read row by row within the pixels. The first plurality of conductive pads 102 in other rows of pixels (e.g., the second row 312) are held at a constant voltage throughout this process, limiting the amount of interference that may come from other rows. Based on this pattern of read-out operations, the first plurality of conductive pads 102 in the first row 310 are transferring a charge to the second IC chip simultaneously (103 of
In some embodiments, a third conductive pad 102c of the first plurality of conductive pads 102 is separate from a fourth conductive pad 102d and a fifth conductive pad 102e. The third conductive pad 102c is spaced from the fourth conductive pad 102d by a third corrugated shield line 316, and a line extending between the fifth conductive pad 102e and the third conductive pad 102c is parallel to a segment of the third corrugated shield line 316. In further embodiments, a first shield node 316a of the third corrugated shield line 316 is directly between the third conductive pad 102c and the fourth conductive pad 102d. In yet further embodiments, the third conductive pad 102c, the fourth conductive pad 102d, and the fifth conductive pad 102e are substantially a same distance away from the first shield node 316a of the third corrugated shield line 316.
As shown in the top layout view 300b of
As shown in the circuit diagram 400 of
As shown in the cross-sectional view 500 of
The application of a bias voltage to the gate electrodes 502 of the transfer transistors 404 forms channels between the photodetectors 402 and the floating diffusion nodes 405, providing a path for a photocurrent to flow. The photocurrent flows from the floating diffusion nodes 405 to the second IC chip 103 through a first interconnect structure 506.
The first interconnect structure 506 comprises contacts 508 extending from the floating diffusion nodes 405. The first interconnect structure 506 further comprises a plurality of wire levels 110a-110c and a plurality of vias 512 alternatingly stacked from the contact 508 to the first plurality of bond contacts 112a (only one of which is shown). The plurality of wire levels 110a-110c and the plurality of vias 512 are alternatingly stacked into conductive paths. The plurality of wire levels 110a-110c provide lateral routing between the plurality of vias 512. The plurality of vias 512 provide vertical routing between the plurality of wire levels 110a-110c.
In some embodiments, one or more additional wire levels are between the first wire level 110a and the third wire level 110c. In some embodiments, the contacts 508, the plurality of wire levels 110a-110c, the plurality of vias 512, or any combination of the foregoing are or comprise polysilicon, copper (e.g., Cu), titanium nitride (e.g., TiN), tungsten (e.g., W), aluminum (e.g., Al), tantalum nitride (e.g., TaN), the like, or any combination of the foregoing. In some embodiments, the first plurality of bond contacts 112a, and the first plurality of conductive pads 102, or any combination of the foregoing are or comprise copper (e.g., Cu), silver (e.g., Ag), gold (e.g., Au), another metal, the like, or any combination of the foregoing. The first corrugated shield line 104 is laterally spaced from the first plurality of conductive pads 102.
The second plurality of bond contacts 112b extend from the second plurality of conductive pads 114 to a second interconnect structure 513. Further, the second interconnect structure 513 extends from the second plurality of bond contacts 112b to the reset transistor 406, the source-follower transistor 408, and the select transistor 410. The second plurality of bond contacts 112b may, for example, be as the first plurality of bond contacts 112a are described. Further, the second interconnect structure 513 may, for example, be as the first interconnect structure 506 is described other than layout and/or numbers of conductive features.
The second interconnect structure 513 is electrically coupled to the ASIC 412 on the third IC chip 418 through a through-substrate via (TSV) 514. The TSV 514 is coupled to the third IC chip 418 through additional M-M and D-D bonding layers 516 at the second bond interface 414. In some embodiments, a second interconnect structure 513 may be or comprise a same material as the first interconnect structure 506. The additional M-M and D-D bonding layers 516 may, for example, be as the first M-M and D-D bonding layer 106 is described other than layout and/or numbers of conductive pads.
In some embodiments, the photodetectors 402 are separated from one another by a backside deep trench isolation (BDTI) structure 520. A backside metal grid (BSMG) 522 overlies the BDTI structure 520 and is surrounded a grid of dielectric material 524. In some embodiments, a barrier layer 523 is between the BSMG 522 and the BDTI structure 520. A plurality of color filters 526 is disposed within the grid of dielectric material 524 and overlies the photodetectors 402. In further embodiments, a plurality of micro-lenses 528 are disposed over the color filters 526. The color filters 526 and the micro-lenses 528 are arranged in a plurality of rows and a plurality of columns, respectively overlying the photodetectors 402 of the pixel array.
Although
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As shown in the cross-sectional and top layout views 1300a-1300b of
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While the method is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.
At 1902, dopants are implanted in a first substrate in a first IC chip to form a photodetector array having a plurality of pixel blocks disposed in rows and columns. See, for example,
At 1904, a first interconnect structure is formed over the first substrate, the first interconnect structure comprising a first plurality of conductive pads surrounded by a first dielectric layer. See, for example,
At 1906, a first plurality of corrugated shield lines are respectively formed directly between the conductive pads and within a single row of the plurality of pixel blocks._See, for example,
At 1908, a second interconnect structure is formed on a second IC chip, the second interconnect structure comprising a second plurality of conductive pads and a second plurality of corrugated shield lines surrounded by a second dielectric layer. See, for example,
At 1910, the first IC chip is turned over and placed on the second chip such that first plurality of conductive pads is facing the second plurality of conductive pads. See, for example,
At 1912, the first IC chip is bonded to the second IC chip at a bonding interface, wherein the second plurality of conductive pads is bonded to the first plurality of conductive pads at the bonding interface, and wherein the first and second plurality of corrugated shield lines isolate portions of the first and second plurality of conductive pads from one another. See, for example,
Therefore, the present disclosure relates to a method of forming an IC device comprising an M-M and D-D bonding layer with corrugated shield lines.
Some embodiments relate to an IC device, including a first IC chip comprising a plurality of pixel blocks respectively including one of a first plurality of conductive pads recessed into a first dielectric layer, the plurality of pixel blocks arranged in rows extending in a first direction and columns extending in a second direction perpendicular to the first direction; a second IC chip bonded to the first IC chip at a bonding interface, where the second IC chip comprises a second plurality of conductive pad recessed into a second dielectric layer and contacting the first plurality of conductive pads along the bonding interface; and a first corrugated shield line having outermost edges set-back along the second direction from outermost edges of a first row of the plurality of pixel blocks, the first corrugated shield line being arranged within the first dielectric layer and laterally separating neighboring ones of the first plurality of conductive pads within the first row of the plurality of pixel blocks.
In other embodiments, the present disclosure relates to an IC device, including a first IC chip; a second IC chip bonded to the first IC chip at a bonding interface; and a first pixel arranged across the first IC chip and the second IC chip and comprising a first photodetector subarray and a second photodetector subarray, wherein the first and second IC chips respectively comprise a first dielectric layer and a second dielectric layer directly contacting at the bonding interface, the first IC chip further comprises a first conductive pad and a first shield node recessed into the first dielectric layer and at the bond interface, the first conductive pad underlies the first photodetector subarray, the first shield node underlies the second photodetector subarray, and a first segment and a second segment of a first corrugated shield line protrude outward from opposing sidewalls of the first shield node to partially surround the first conductive pad.
In yet other embodiments, the present disclosure relates to a method of forming an integrated circuit (IC) device including implanting dopants in a first substrate in a first IC chip to form a photodetector array; forming a first interconnect structure over the first substrate, the first interconnect structure comprising a first plurality of conductive pads surrounded by a first dielectric layer; forming a first plurality of corrugated shield lines directly between the conductive pads; forming a second interconnect structure on a second IC chip, the second interconnect structure comprising a second plurality of conductive pads and a second plurality of corrugated shield lines surrounded by a second dielectric layer; turning the first IC chip over and placing the first IC chip on the second IC chip such that first plurality of conductive pads is facing the second plurality of conductive pads; and bonding the first IC chip to the second IC chip at a bonding interface, wherein the second plurality of conductive pads is bonded to the first plurality of conductive pads at the bonding interface, and wherein the first and second plurality of corrugated shield lines isolate portions of the first and second plurality of conductive pads from one another.
It will be appreciated that in this written description, as well as in the claims below, the terms “first”, “second”, “second”, “third” etc. are merely generic identifiers used for ease of description to distinguish between different elements of a figure or a series of figures. In and of themselves, these terms do not imply any temporal ordering or structural proximity for these elements, and are not intended to be descriptive of corresponding elements in different illustrated embodiments and/or un-illustrated embodiments. For example, “a first dielectric layer” described in connection with a first figure may not necessarily correspond to a “first dielectric layer” described in connection with another figure, and may not necessarily correspond to a “first dielectric layer” in an un-illustrated embodiment.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
