Adam J. Wright

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bi-specific probes to enable the use of single-cell samples as sing...
- Patent number 12,153,043
- Issue date Nov 26, 2024
- Becton, Dickinson and Company
- Jody Martin
- G01 - MEASURING TESTING
Information Patent Grant
Methods and systems for providing epitope tagged biomolecules
- Patent number 11,315,661
- Issue date Apr 26, 2022
- Becton, Dickinson and Company
- Jody Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuits with in-field diagnostic and repair capabilities
- Patent number 11,281,195
- Issue date Mar 22, 2022
- Intel Corporation
- Kenneth T. Daxer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for a low-cost semiconductor test interface system
- Patent number 8,786,301
- Issue date Jul 22, 2014
- Altera Corporation
- Adam J. Wright
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for minimizing skew between signals
- Patent number 8,779,754
- Issue date Jul 15, 2014
- Altera Corporation
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for serial scan test data delivery
- Patent number 8,543,876
- Issue date Sep 24, 2013
- Altera Corporation
- Adam J. Wright
- G01 - MEASURING TESTING
Information Patent Grant
Circuits and method for bypassing a static configuration in a progr...
- Patent number 7,940,082
- Issue date May 10, 2011
- Altera Corporation
- Adam J. Wright
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for minimizing skew between signals
- Patent number 7,884,619
- Issue date Feb 8, 2011
- Altera Corporation
- Yan Chong
- G01 - MEASURING TESTING
Information Patent Grant
High speed programming of programmable logic devices
- Patent number 7,795,909
- Issue date Sep 14, 2010
- Altera Corporation
- Kenneth T. Daxer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for a low-cost semiconductor test interface system
- Patent number 7,768,280
- Issue date Aug 3, 2010
- Altera Corporation
- Adam J. Wright
- G01 - MEASURING TESTING
Information Patent Grant
Functional failure analysis techniques for programmable integrated...
- Patent number 7,685,485
- Issue date Mar 23, 2010
- Altera Corporation
- Binh Vo
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for quantifying and minimizing skew between si...
- Patent number 7,671,579
- Issue date Mar 2, 2010
- Altera Corporation
- Yan Chong
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for debugging semiconductor devices
- Patent number 7,546,507
- Issue date Jun 9, 2009
- Altera Corporation
- Adam J. Wright
- G01 - MEASURING TESTING
Information Patent Grant
Automatic test configuration generation facilitating repair of prog...
- Patent number 7,409,669
- Issue date Aug 5, 2008
- Altera Corporation
- Jayabrata Ghosh Dastidar
- G01 - MEASURING TESTING
Information Patent Grant
Methods and structures for protecting programming data for a progra...
- Patent number 7,265,573
- Issue date Sep 4, 2007
- Altera Corporation
- Adam Wright
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for loading configuration data into a configuration word reg...
- Patent number 7,237,106
- Issue date Jun 26, 2007
- Altera Corporation
- Paul Tracy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for testing interconnect bridging faults in an...
- Patent number 7,103,813
- Issue date Sep 5, 2006
- Altera Corporation
- Paul Tracy
- G01 - MEASURING TESTING
Information Patent Grant
Techniques for automatically generating tests for programmable circ...
- Patent number 7,024,327
- Issue date Apr 4, 2006
- Altera Corporation
- Jayabrata Ghosh Dastidar
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for laser marking of integrated circuit faults
- Patent number 7,020,582
- Issue date Mar 28, 2006
- Altera Corporation
- John M. Dicosola
- G01 - MEASURING TESTING
Information Patent Grant
Method of creating a mask-programmed logic device from a pre-existi...
- Patent number 6,938,236
- Issue date Aug 30, 2005
- Altera Corporation
- Jonathan Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tool to reconfigure pin connections between a DUT and a tester
- Patent number 6,625,771
- Issue date Sep 23, 2003
- Altera Corporation
- Adam Wright
- G01 - MEASURING TESTING
Information Patent Grant
Tool to reconfigure pin connections between a DUT and a tester
- Patent number 6,247,155
- Issue date Jun 12, 2001
- Altera Corporation
- Adam Wright
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for generating configuration and test files fo...
- Patent number 6,112,020
- Issue date Aug 29, 2000
- Altera Corporation
- Adam Wright
- G01 - MEASURING TESTING
Information Patent Grant
Tool to reconfigure pin connections between a dut and a tester
- Patent number 5,909,450
- Issue date Jun 1, 1999
- Altera Corporation
- Adam Wright
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SORTING OF MRNA AND/OR ABSEQ CONTAINING BARCODED BEADS BY FLOW
- Publication number 20250066843
- Publication date Feb 27, 2025
- Becton, Dickinson and Company
- Jody Martin
- C12 - BIOCHEMISTRY BEER SPIRITS WINE VINEGAR MICROBIOLOGY ENZYMOLOGY MUTATION...
Information Patent Application
MULTIPLEXED PROTEOMICS ANALYSIS USING OLIGONUCLEOTIDE-CONJUGATED AN...
- Publication number 20240369545
- Publication date Nov 7, 2024
- Becton, Dickinson and Company
- Adam Thomas Wright
- G01 - MEASURING TESTING
Information Patent Application
HIGH-THROUGHPUT FLOW CYTOMETRY ANALYSIS OF HIGHLY MULTIPLEXED SAMPL...
- Publication number 20230333105
- Publication date Oct 19, 2023
- Becton, Dickinson and Company
- Jody Martin
- G01 - MEASURING TESTING
Information Patent Application
BI-SPECIFIC PROBES TO ENABLE THE USE OF SINGLE-CELL SAMPLES AS SING...
- Publication number 20210263019
- Publication date Aug 26, 2021
- Becton, Dickinson and Company
- Jody Martin
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUITS WITH IN-FIELD DIAGNOSTIC AND REPAIR CAPABILITES
- Publication number 20190101906
- Publication date Apr 4, 2019
- Intel Corporation
- Kenneth T. Daxer
- G05 - CONTROLLING REGULATING
Information Patent Application
METHODS AND SYSTEMS FOR PROVIDING EPITOPE TAGGED BIOMOLECULES
- Publication number 20180232484
- Publication date Aug 16, 2018
- Becton, Dickinson and Company
- Jody Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS
- Publication number 20110221497
- Publication date Sep 15, 2011
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Functional failure analysis techniques for programmable integrated...
- Publication number 20050022085
- Publication date Jan 27, 2005
- Altera Corporation
- Binh Vo
- G01 - MEASURING TESTING
Information Patent Application
Tool to reconfigure pin connections between a DUT and a tester
- Publication number 20020019963
- Publication date Feb 14, 2002
- Adam Wright
- G01 - MEASURING TESTING

Adam J. Wright

Person

Patents Grantslast 30 patents

Bi-specific probes to enable the use of single-cell samples as sing...

Methods and systems for providing epitope tagged biomolecules

Integrated circuits with in-field diagnostic and repair capabilities

Apparatus for a low-cost semiconductor test interface system

Method and apparatus for minimizing skew between signals

Method and apparatus for serial scan test data delivery

Circuits and method for bypassing a static configuration in a progr...

Method and apparatus for minimizing skew between signals

High speed programming of programmable logic devices

Apparatus for a low-cost semiconductor test interface system

Functional failure analysis techniques for programmable integrated...

Method and apparatus for quantifying and minimizing skew between si...

Method and apparatus for debugging semiconductor devices

Automatic test configuration generation facilitating repair of prog...

Methods and structures for protecting programming data for a progra...

System for loading configuration data into a configuration word reg...

Method and apparatus for testing interconnect bridging faults in an...

Techniques for automatically generating tests for programmable circ...

Methods and apparatus for laser marking of integrated circuit faults

Method of creating a mask-programmed logic device from a pre-existi...

Tool to reconfigure pin connections between a DUT and a tester

Tool to reconfigure pin connections between a DUT and a tester

Apparatus and method for generating configuration and test files fo...

Tool to reconfigure pin connections between a dut and a tester

Patents Applicationslast 30 patents

SORTING OF MRNA AND/OR ABSEQ CONTAINING BARCODED BEADS BY FLOW

MULTIPLEXED PROTEOMICS ANALYSIS USING OLIGONUCLEOTIDE-CONJUGATED AN...

HIGH-THROUGHPUT FLOW CYTOMETRY ANALYSIS OF HIGHLY MULTIPLEXED SAMPL...

BI-SPECIFIC PROBES TO ENABLE THE USE OF SINGLE-CELL SAMPLES AS SING...

INTEGRATED CIRCUITS WITH IN-FIELD DIAGNOSTIC AND REPAIR CAPABILITES

METHODS AND SYSTEMS FOR PROVIDING EPITOPE TAGGED BIOMOLECULES

METHOD AND APPARATUS FOR MINIMIZING SKEW BETWEEN SIGNALS

Functional failure analysis techniques for programmable integrated...

Tool to reconfigure pin connections between a DUT and a tester