Adam Malamy

Person

Winchester, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for testing cache RAM residing on a microproce...
- Patent number 5,781,721
- Issue date Jul 14, 1998
- Sun Microsystems, Inc.
- Norman M. Hayes
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for a coherent copy-back buffer in a multipres...
- Patent number 5,708,792
- Issue date Jan 13, 1998
- Sun Microsystems, Inc.
- Norman M. Hayes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory system with independently accessible subdivided cache...
- Patent number 5,675,765
- Issue date Oct 7, 1997
- Sun Microsystems, Inc.
- Adam Malamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for identifying faults within a system
- Patent number 5,570,376
- Issue date Oct 29, 1996
- Sun Microsystems, Inc.
- Ramachandra P. Kunda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple bank column redundancy intialization controller for cache RAM
- Patent number 5,537,665
- Issue date Jul 16, 1996
- Sun Microsystems, Inc.
- Rajiv N. Patel
- G11 - INFORMATION STORAGE
Information Patent Grant
Instruction and data cache with a shared TLB for split accesses and...
- Patent number 5,440,707
- Issue date Aug 8, 1995
- Sun Microsystems, Inc.
- Norman M. Hayes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for implementing a pseudo-LRU cache memory re...
- Patent number 5,353,425
- Issue date Oct 4, 1994
- Sun Microsystems, Inc.
- Adam Malamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache miss buffer adapted to satisfy read requests to portions of a...
- Patent number 5,353,426
- Issue date Oct 4, 1994
- Sun Microsystems, Inc.
- Rajiv N. Patel
- G06 - COMPUTING CALCULATING COUNTING

Adam Malamy

Person

Patents Grantslast 30 patents

Method and apparatus for testing cache RAM residing on a microproce...

Method and apparatus for a coherent copy-back buffer in a multipres...

Cache memory system with independently accessible subdivided cache...

Method and apparatus for identifying faults within a system

Multiple bank column redundancy intialization controller for cache RAM

Instruction and data cache with a shared TLB for split accesses and...

Methods and apparatus for implementing a pseudo-LRU cache memory re...

Cache miss buffer adapted to satisfy read requests to portions of a...