Adi Srinivasan

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Thermal simulation using adaptive 3D and hierarchical grid mechanisms
- Patent number 8,286,111
- Issue date Oct 9, 2012
- Gradient Design Automation Inc.
- Rajit Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Transient thermal analysis
- Patent number 8,019,580
- Issue date Sep 13, 2011
- Gradient Design Automation Inc.
- Rajit Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thermally aware design modification
- Patent number 7,823,102
- Issue date Oct 26, 2010
- Gradient Design Automation Inc.
- Rajit Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for using full-chip thermal analysis of semico...
- Patent number 7,353,471
- Issue date Apr 1, 2008
- Gradient Design Automation Inc.
- Rajit Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit optimization for minimum path timing violations
- Patent number 7,222,318
- Issue date May 22, 2007
- Sequence Design, Inc.
- Adi Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for determining load capacitance
- Patent number 7,003,741
- Issue date Feb 21, 2006
- Sequence Design, Inc.
- Adi Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Function block architecture for gate array and method for forming a...
- Patent number 6,954,917
- Issue date Oct 11, 2005
- Lightspeed Semiconductor Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for optimal driver selection
- Patent number 6,754,877
- Issue date Jun 22, 2004
- Sequence Design, Inc.
- Adi Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for determining a zero-skew buffer insertion point
- Patent number 6,701,507
- Issue date Mar 2, 2004
- Sequence Design, Inc.
- Adi Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for match delay buffer insertion
- Patent number 6,701,506
- Issue date Mar 2, 2004
- Sequence Design, Inc.
- Adi Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit optimization for minimum path timing violations
- Patent number 6,701,505
- Issue date Mar 2, 2004
- Sequence Design, Inc.
- Adi Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for balanced-delay clock tree insertion
- Patent number 6,698,006
- Issue date Feb 24, 2004
- Sequence Design, Inc.
- Adi Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Function block architecture for gate array
- Patent number 6,690,194
- Issue date Feb 10, 2004
- Lightspeed Semiconductor Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling and observing data in a logic...
- Patent number 6,611,932
- Issue date Aug 26, 2003
- Lightspeed Semiconductor Corporation
- Dana How
- G01 - MEASURING TESTING
Information Patent Grant
Asic routing architecture
- Patent number 6,242,767
- Issue date Jun 5, 2001
- LightSpeed Semiconductor Corp.
- Dana How
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for controlling and observing data in a logic...
- Patent number 6,223,313
- Issue date Apr 24, 2001
- Lightspeed Semiconductor Corporation
- Dana How
- G01 - MEASURING TESTING
Information Patent Grant
Function block architecture for gate array
- Patent number 6,014,038
- Issue date Jan 11, 2000
- Lightspeed Semiconductor Corporation
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable interconnect architecture using fewer storage cells th...
- Patent number 5,406,138
- Issue date Apr 11, 1995
- Aptix Corporation
- Adi Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory cell with user-selectable logic state on power-up
- Patent number 5,400,294
- Issue date Mar 21, 1995
- Aptix Corporation
- Adi Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage random-access memory cell incorporation level shifter
- Patent number 5,367,482
- Issue date Nov 22, 1994
- Aptix Corporation
- Ta-Pen Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Reprogrammable interconnect architecture using fewer storage cells...
- Patent number 5,319,261
- Issue date Jun 7, 1994
- Aptix Corporation
- Adi Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-voltage five-transistor static random access memory cell
- Patent number 5,315,545
- Issue date May 24, 1994
- Aptix Corporation
- Ta-Pan Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory cell with single logic-high voltage lev...
- Patent number 5,301,147
- Issue date Apr 5, 1994
- Aptix Corporation
- Ta-Pen Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Low current, fast, CMOS static pullup circuit for static random-acc...
- Patent number 5,264,741
- Issue date Nov 23, 1993
- Aptix Corporation
- Adi Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory cell with known state on power-up
- Patent number 5,257,239
- Issue date Oct 26, 1993
- Aptix Corporation
- Ta-Pen Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage random-access memory cell incorporating level shifter
- Patent number 5,239,503
- Issue date Aug 24, 1993
- Aptix Corporation
- Ta-Pen Guo
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Thermal Simulation Using Adaptive 3D and Hierarchical Grid Mechanisms
- Publication number 20090024347
- Publication date Jan 22, 2009
- Rajit Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Thermally Aware Design Modification
- Publication number 20090019411
- Publication date Jan 15, 2009
- Rajit Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR USING FULL-CHIP THERMAL ANALYSIS OF SEMICO...
- Publication number 20080141192
- Publication date Jun 12, 2008
- RAJIT CHANDRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for optimal driver selection
- Publication number 20040210857
- Publication date Oct 21, 2004
- Adi Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit optimization for minimum path timing violations
- Publication number 20040088664
- Publication date May 6, 2004
- Sequence Design, Inc.
- Adi Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Function block architecture for gate array
- Publication number 20030214324
- Publication date Nov 20, 2003
- Dana How
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for controlling and observing data in a logic...
- Publication number 20020073369
- Publication date Jun 13, 2002
- LightSpeed Semiconductor Corporation
- Dana How
- G01 - MEASURING TESTING

Adi Srinivasan

Person

Patents Grantslast 30 patents

Thermal simulation using adaptive 3D and hierarchical grid mechanisms

Transient thermal analysis

Thermally aware design modification

Method and apparatus for using full-chip thermal analysis of semico...

Circuit optimization for minimum path timing violations

Method for determining load capacitance

Function block architecture for gate array and method for forming a...

Method for optimal driver selection

Method for determining a zero-skew buffer insertion point

Method for match delay buffer insertion

Circuit optimization for minimum path timing violations

Method for balanced-delay clock tree insertion

Function block architecture for gate array

Method and apparatus for controlling and observing data in a logic...

Asic routing architecture

Method and apparatus for controlling and observing data in a logic...

Function block architecture for gate array

Programmable interconnect architecture using fewer storage cells th...

Memory cell with user-selectable logic state on power-up

High voltage random-access memory cell incorporation level shifter

Reprogrammable interconnect architecture using fewer storage cells...

High-voltage five-transistor static random access memory cell

Static random access memory cell with single logic-high voltage lev...

Low current, fast, CMOS static pullup circuit for static random-acc...

Memory cell with known state on power-up

High voltage random-access memory cell incorporating level shifter

Patents Applicationslast 30 patents

Thermal Simulation Using Adaptive 3D and Hierarchical Grid Mechanisms

Thermally Aware Design Modification

METHOD AND APPARATUS FOR USING FULL-CHIP THERMAL ANALYSIS OF SEMICO...

Method for optimal driver selection

Circuit optimization for minimum path timing violations

Function block architecture for gate array

Method and apparatus for controlling and observing data in a logic...