Akash AGRAWAL

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bonding of laminates with electrical interconnects
- Patent number 10,790,222
- Issue date Sep 29, 2020
- Invensas Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-surface edge pads for vertical mount packages and methods of...
- Patent number 10,354,945
- Issue date Jul 16, 2019
- Invensas Corporation
- Rajesh Katkar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Bonding of laminates with electrical interconnects
- Patent number 10,283,445
- Issue date May 7, 2019
- Invensas Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level packaging using wire bond wires in place of a redistrib...
- Patent number 10,008,469
- Issue date Jun 26, 2018
- Invensas Corporation
- Rajesh Katkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and structures to repair device warpage
- Patent number 9,859,234
- Issue date Jan 2, 2018
- Invensas Corporation
- Cyprian Emeka Uzoh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out wafer-level packaging using metal foil lamination
- Patent number 9,847,238
- Issue date Dec 19, 2017
- Invensas Corporation
- Xuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit assemblies with rigid layers used for protection...
- Patent number 9,824,974
- Issue date Nov 21, 2017
- Invensas Corporation
- Guilian Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced density assembly having microelectronic packages mounted a...
- Patent number 9,728,524
- Issue date Aug 8, 2017
- Invensas Corporation
- Min Tao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fan-out wafer-level packaging using metal foil lamination
- Patent number 9,646,946
- Issue date May 9, 2017
- Invensas Corporation
- Xuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit assemblies with rigid layers used for protection...
- Patent number 9,548,273
- Issue date Jan 17, 2017
- Invensas Corporation
- Guilian Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level packages with mechanically decoupled fan-in and fan-out...
- Patent number 9,543,277
- Issue date Jan 10, 2017
- Invensas Corporation
- Bongsub Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer-level packaging using wire bond wires in place of a redistrib...
- Patent number 9,502,372
- Issue date Nov 22, 2016
- Invensas Corporation
- Rajesh Katkar
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SUBSTRATE FRAME DESIGN FOR THREE-DIMENSIONAL STACKED ELECTRONIC ASS...
- Publication number 20230420351
- Publication date Dec 28, 2023
- Applied Materials, Inc.
- Akash Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVALUATING ON-DEVICE MACHINE LEARNING MODEL(S) BASED ON PERFORMANCE...
- Publication number 20220309389
- Publication date Sep 29, 2022
- Google LLC
- Dragan Zivkovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVALUATING NEW FEATURE(S) FOR CLIENT DEVICE(S) BASED ON PERFORMANCE...
- Publication number 20220308975
- Publication date Sep 29, 2022
- Google LLC
- Dragan Zivkovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BONDING OF LAMINATES WITH ELECTRICAL INTERCONNECTS
- Publication number 20190221510
- Publication date Jul 18, 2019
- Invensas Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bonding of Laminates with Electrical Interconnects
- Publication number 20180114747
- Publication date Apr 26, 2018
- Invensas Corporation
- Javier A. Delacruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-surface edge pads for vertical mount packages and methods of...
- Publication number 20180040544
- Publication date Feb 8, 2018
- Invensas Corporation
- Rajesh Emeka Katkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fan-Out Wafer-Level Packaging Using Metal Foil Lamination
- Publication number 20170170031
- Publication date Jun 15, 2017
- Invensas Corporation
- Xuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FAN-OUT WAFER-LEVEL PACKAGING USING METAL FOIL LAMINATION
- Publication number 20170103957
- Publication date Apr 13, 2017
- Invensas Corporation
- Xuan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT ASSEMBLIES WITH RIGID LAYERS USED FOR PROTECTION...
- Publication number 20170084539
- Publication date Mar 23, 2017
- Invensas Corporation
- Guilian GAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIB...
- Publication number 20170069591
- Publication date Mar 9, 2017
- Invensas Corporation
- Rajesh KATKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND STRUCTURES TO REPAIR DEVICE WARPAGE
- Publication number 20170040270
- Publication date Feb 9, 2017
- Invensas Corporation
- Cyprian Emeka Uzoh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIB...
- Publication number 20160322326
- Publication date Nov 3, 2016
- Invensas Corporation
- Rajesh KATKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT ASSEMBLIES WITH RIGID LAYERS USED FOR PROTECTION...
- Publication number 20160163650
- Publication date Jun 9, 2016
- Invensas Corporation
- Guilian GAO
- H01 - BASIC ELECTRIC ELEMENTS

Akash AGRAWAL

Person

Patents Grantslast 30 patents

Bonding of laminates with electrical interconnects

Multi-surface edge pads for vertical mount packages and methods of...

Bonding of laminates with electrical interconnects

Wafer-level packaging using wire bond wires in place of a redistrib...

Methods and structures to repair device warpage

Fan-out wafer-level packaging using metal foil lamination

Integrated circuit assemblies with rigid layers used for protection...

Enhanced density assembly having microelectronic packages mounted a...

Fan-out wafer-level packaging using metal foil lamination

Integrated circuit assemblies with rigid layers used for protection...

Wafer level packages with mechanically decoupled fan-in and fan-out...

Wafer-level packaging using wire bond wires in place of a redistrib...

Patents Applicationslast 30 patents

SUBSTRATE FRAME DESIGN FOR THREE-DIMENSIONAL STACKED ELECTRONIC ASS...

EVALUATING ON-DEVICE MACHINE LEARNING MODEL(S) BASED ON PERFORMANCE...

EVALUATING NEW FEATURE(S) FOR CLIENT DEVICE(S) BASED ON PERFORMANCE...

BONDING OF LAMINATES WITH ELECTRICAL INTERCONNECTS

Bonding of Laminates with Electrical Interconnects

Multi-surface edge pads for vertical mount packages and methods of...

Fan-Out Wafer-Level Packaging Using Metal Foil Lamination

FAN-OUT WAFER-LEVEL PACKAGING USING METAL FOIL LAMINATION

INTEGRATED CIRCUIT ASSEMBLIES WITH RIGID LAYERS USED FOR PROTECTION...

WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIB...

METHODS AND STRUCTURES TO REPAIR DEVICE WARPAGE

WAFER-LEVEL PACKAGING USING WIRE BOND WIRES IN PLACE OF A REDISTRIB...

INTEGRATED CIRCUIT ASSEMBLIES WITH RIGID LAYERS USED FOR PROTECTION...