Albert Fazio

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Three dimensional circuit systems and methods having memory hierarc...
- Patent number 11,789,641
- Issue date Oct 17, 2023
- Intel Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable bandwidth non-volatile memory
- Patent number 11,010,061
- Issue date May 18, 2021
- Intel Corporation
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory preset adjustment based on adaptive calibration
- Patent number 10,679,698
- Issue date Jun 9, 2020
- Intel Corporation
- Prashant S. Damle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable bandwidth non-volatile memory
- Patent number 10,331,360
- Issue date Jun 25, 2019
- Intel Corporation
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system to determine access information for a...
- Patent number 8,649,212
- Issue date Feb 11, 2014
- Intel Corporation
- Derchang Kau
- G11 - INFORMATION STORAGE
Information Patent Grant
Data error recovery in non-volatile memory
- Patent number 8,291,297
- Issue date Oct 16, 2012
- Intel Corporation
- Richard Coulson
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory cell having reduced floating gate to floating gate cou...
- Patent number 7,465,625
- Issue date Dec 16, 2008
- Been-jon K. Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory cell having reduced floating gate to floating gate cou...
- Patent number 7,348,618
- Issue date Mar 25, 2008
- Intel Corporation
- Been-jon K. Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MEMS probe based memory
- Patent number 7,050,320
- Issue date May 23, 2006
- Intel Corporation
- Stefan Lai
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory cell and method of fabrication
- Patent number 6,943,071
- Issue date Sep 13, 2005
- Intel Corporation
- Albert Fazio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated memory cell and method of fabrication
- Patent number 6,518,618
- Issue date Feb 11, 2003
- Intel Corporation
- Albert Fazio
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and circuitry for storing discrete amounts of charge in a si...
- Patent number 6,091,618
- Issue date Jul 18, 2000
- Intel Corporation
- Albert Fazio
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuitry for storing discrete amounts of charge in a si...
- Patent number 5,892,710
- Issue date Apr 6, 1999
- Intel Corporation
- Albert Fazio
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing scheme for flash memory with multilevel cells
- Patent number 5,828,616
- Issue date Oct 27, 1998
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Deselected word line that floats during MLC programming of a flash...
- Patent number 5,801,991
- Issue date Sep 1, 1998
- Intel Corporation
- Stephen N. Keeney
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing scheme for flash memory with multilevel cells
- Patent number 5,748,546
- Issue date May 5, 1998
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory device having a page mode of operation
- Patent number 5,742,543
- Issue date Apr 21, 1998
- Intel Corporation
- Albert Fazio
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming flash memory using data stream analysis
- Patent number 5,737,265
- Issue date Apr 7, 1998
- Intel Corporation
- Gregory E. Atwood
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming flash memory using predictive learning methods
- Patent number 5,729,489
- Issue date Mar 17, 1998
- Intel Corporation
- Albert Fazio
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming flash memory using distributed learning methods
- Patent number 5,701,266
- Issue date Dec 23, 1997
- Intel Corporation
- Albert Fazio
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming flash memory using strict ordering of states
- Patent number 5,677,869
- Issue date Oct 14, 1997
- Intel Corporation
- Albert Fazio
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuitry for storing discrete amounts of charge in a si...
- Patent number 5,566,125
- Issue date Oct 15, 1996
- Intel Corporation
- Albert Fazio
- G11 - INFORMATION STORAGE
Information Patent Grant
High precision voltage regulation circuit for programming multiple...
- Patent number 5,546,042
- Issue date Aug 13, 1996
- Intel Corporation
- Kerry D. Tedrow
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method and apparatus for verifying the programming of multi-level f...
- Patent number 5,523,972
- Issue date Jun 4, 1996
- Intel Corporation
- Mamun Rashid
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for sensing the state of floating gate memory...
- Patent number 5,508,958
- Issue date Apr 16, 1996
- Intel Corporation
- Albert Fazio
- G11 - INFORMATION STORAGE
Information Patent Grant
High precision voltage regulation circuit for programming multileve...
- Patent number 5,497,119
- Issue date Mar 5, 1996
- Intel Corporation
- Kerry D. Tedrow
- G05 - CONTROLLING REGULATING
Information Patent Grant
Error management processes for flash EEPROM memory arrays
- Patent number 5,475,693
- Issue date Dec 12, 1995
- Intel Corporation
- Mark Christopherson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling the output current provided by...
- Patent number 5,455,794
- Issue date Oct 3, 1995
- Intel Corporation
- Jahanshir J. Javanifard
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for controlling the output current provided by...
- Patent number 5,442,586
- Issue date Aug 15, 1995
- Intel Corporation
- Jahanshir J. Javanifard
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuitry for storing discrete amounts of charge in a si...
- Patent number 5,440,505
- Issue date Aug 8, 1995
- Intel Corporation
- Albert Fazio
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
STACKED TWO-LEVEL BACKEND MEMORY
- Publication number 20220415892
- Publication date Dec 29, 2022
- Intel Corporation
- Wilfred Gomes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Three Dimensional Circuit Systems And Methods Having Memory Hierarc...
- Publication number 20220405005
- Publication date Dec 22, 2022
- Intel Corporation
- Scott Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE BANDWIDTH NON-VOLATILE MEMORY
- Publication number 20190332278
- Publication date Oct 31, 2019
- Intel Corporation
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PRESET ADJUSTMENT BASED ON ADAPTIVE CALIBRATION
- Publication number 20190043571
- Publication date Feb 7, 2019
- Intel Corporation
- Prashant S. DAMLE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE BANDWIDTH NON-VOLATILE MEMORY
- Publication number 20180088834
- Publication date Mar 29, 2018
- Intel Corporation
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM TO DETERMINE ACCESS INFORMATION FOR A...
- Publication number 20120075924
- Publication date Mar 29, 2012
- Derchang Kau
- G11 - INFORMATION STORAGE
Information Patent Application
Data error recovery in non-volatile memory
- Publication number 20100162084
- Publication date Jun 24, 2010
- Richard Coulson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flash memory cell having reduced floating gate to floating gate cou...
- Publication number 20070037350
- Publication date Feb 15, 2007
- Been-jon K. Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flash memory cell having reduced floating gate to floating gate cou...
- Publication number 20060228858
- Publication date Oct 12, 2006
- Been-jon K. Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated memory cell and method of fabrication
- Publication number 20020149050
- Publication date Oct 17, 2002
- Albert Fazio
- H01 - BASIC ELECTRIC ELEMENTS

Albert Fazio

Person

Patents Grantslast 30 patents

Three dimensional circuit systems and methods having memory hierarc...

Scalable bandwidth non-volatile memory

Memory preset adjustment based on adaptive calibration

Scalable bandwidth non-volatile memory

Method, apparatus and system to determine access information for a...

Data error recovery in non-volatile memory

Flash memory cell having reduced floating gate to floating gate cou...

Flash memory cell having reduced floating gate to floating gate cou...

MEMS probe based memory

Integrated memory cell and method of fabrication

Integrated memory cell and method of fabrication

Method and circuitry for storing discrete amounts of charge in a si...

Method and circuitry for storing discrete amounts of charge in a si...

Sensing scheme for flash memory with multilevel cells

Deselected word line that floats during MLC programming of a flash...

Sensing scheme for flash memory with multilevel cells

Flash memory device having a page mode of operation

Programming flash memory using data stream analysis

Programming flash memory using predictive learning methods

Programming flash memory using distributed learning methods

Programming flash memory using strict ordering of states

Method and circuitry for storing discrete amounts of charge in a si...

High precision voltage regulation circuit for programming multiple...

Method and apparatus for verifying the programming of multi-level f...

Method and apparatus for sensing the state of floating gate memory...

High precision voltage regulation circuit for programming multileve...

Error management processes for flash EEPROM memory arrays

Method and apparatus for controlling the output current provided by...

Method and apparatus for controlling the output current provided by...

Method and circuitry for storing discrete amounts of charge in a si...

Patents Applicationslast 30 patents

STACKED TWO-LEVEL BACKEND MEMORY

Three Dimensional Circuit Systems And Methods Having Memory Hierarc...

SCALABLE BANDWIDTH NON-VOLATILE MEMORY

MEMORY PRESET ADJUSTMENT BASED ON ADAPTIVE CALIBRATION

SCALABLE BANDWIDTH NON-VOLATILE MEMORY

METHOD, APPARATUS AND SYSTEM TO DETERMINE ACCESS INFORMATION FOR A...

Data error recovery in non-volatile memory

Flash memory cell having reduced floating gate to floating gate cou...

Flash memory cell having reduced floating gate to floating gate cou...

Integrated memory cell and method of fabrication