Alexander Ishii

Person

Princeton, NJ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Resonant clock distribution network architecture for tracking param...
- Patent number 9,041,451
- Issue date May 26, 2015
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resonant clock distribution network architecture with programmable...
- Patent number 8,659,338
- Issue date Feb 25, 2014
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture for controlling clock characteristics
- Patent number 8,593,183
- Issue date Nov 26, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture for operating resonant clock network in conventional mode
- Patent number 8,502,569
- Issue date Aug 6, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resonant clock and interconnect architecture for digital devices wi...
- Patent number 8,461,873
- Issue date Jun 11, 2013
- Cyclos Semiconductor, Inc.
- Alexander T. Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for frequency-scaled operation in resonant clock distr...
- Patent number 8,400,192
- Issue date Mar 19, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture for adjusting natural frequency in resonant clock dist...
- Patent number 8,368,450
- Issue date Feb 5, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Architecture for single-stepping in resonant clock distribution net...
- Patent number 8,362,811
- Issue date Jan 29, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resonant clock distribution network architecture for tracking param...
- Patent number 8,358,163
- Issue date Jan 22, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for selecting natural frequency in resonant clock distributi...
- Patent number 8,339,209
- Issue date Dec 25, 2012
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Resonant clock and interconnect architecture for digital devices wi...
- Patent number 7,973,565
- Issue date Jul 5, 2011
- Cyclos Semiconductor, Inc.
- Alexander Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast round robin priority port scheduler for high capacity ATM swit...
- Patent number 6,556,571
- Issue date Apr 29, 2003
- NEC USA, Inc.
- Sharif M. Shahrier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimal buffer management scheme with dynamic queue length threshol...
- Patent number 6,424,622
- Issue date Jul 23, 2002
- NEC USA, Inc.
- Ruixue Fan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Time-based scheduler architecture and method for ATM networks
- Patent number 6,389,019
- Issue date May 14, 2002
- NEC USA, Inc.
- Ruixue Fan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Retiming gated-clocks and precharged circuit structures
- Patent number 5,644,499
- Issue date Jul 1, 1997
- NEC USA, Inc.
- Alexander T. Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control architecture for ATM networks
- Patent number 5,448,567
- Issue date Sep 5, 1995
- NEC Research Institute, Inc.
- Rajiv Dighe
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Resonant Clock Distribution Network Architecture for Tracking Param...
- Publication number 20140015585
- Publication date Jan 16, 2014
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture for Single-Stepping in Resonant Clock Distribution Net...
- Publication number 20140002175
- Publication date Jan 2, 2014
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture for Adjusting Natural Frequency in Resonant Clock Dist...
- Publication number 20130328608
- Publication date Dec 12, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Selecting Natural Frequency in Resonant Clock Distributi...
- Publication number 20130194018
- Publication date Aug 1, 2013
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resonant Clock And Interconnect Architecture For Digital Devices Wi...
- Publication number 20110210761
- Publication date Sep 1, 2011
- Alexander T. Ishii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE WITH PROGRAMMABLE...
- Publication number 20110140753
- Publication date Jun 16, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR ADJUSTING NATURAL FREQUENCY IN RESONANT CLOCK DIST...
- Publication number 20110090018
- Publication date Apr 21, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR FREQUENCY-SCALED OPERATION IN RESONANT CLOCK DISTR...
- Publication number 20110090019
- Publication date Apr 21, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR CONTROLLING CLOCK CHARACTERISTICS
- Publication number 20110084736
- Publication date Apr 14, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR SELECTING NATURAL FREQUENCY IN RESONANT CLOCK DISTRIBUTI...
- Publication number 20110084772
- Publication date Apr 14, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR SINGLE-STEPPING IN RESONANT CLOCK DISTRIBUTION NET...
- Publication number 20110084773
- Publication date Apr 14, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR OPERATING RESONANT CLOCK NETWORK IN CONVENTIONAL MODE
- Publication number 20110084774
- Publication date Apr 14, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE FOR TRACKING PARAM...
- Publication number 20110084775
- Publication date Apr 14, 2011
- Cyclos Semiconductor, Inc.
- Marios C. Papaefthymiou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESONANT CLOCK AND INTERCONNECT ARCHITECTURE FOR DIGITAL DEVICES WI...
- Publication number 20090027085
- Publication date Jan 29, 2009
- Cyclos Semiconductor, Inc.
- Alexander T. Ishii
- G06 - COMPUTING CALCULATING COUNTING

Alexander Ishii

Person

Patents Grantslast 30 patents

Resonant clock distribution network architecture for tracking param...

Resonant clock distribution network architecture with programmable...

Architecture for controlling clock characteristics

Architecture for operating resonant clock network in conventional mode

Resonant clock and interconnect architecture for digital devices wi...

Architecture for frequency-scaled operation in resonant clock distr...

Architecture for adjusting natural frequency in resonant clock dist...

Architecture for single-stepping in resonant clock distribution net...

Resonant clock distribution network architecture for tracking param...

Method for selecting natural frequency in resonant clock distributi...

Resonant clock and interconnect architecture for digital devices wi...

Fast round robin priority port scheduler for high capacity ATM swit...

Optimal buffer management scheme with dynamic queue length threshol...

Time-based scheduler architecture and method for ATM networks

Retiming gated-clocks and precharged circuit structures

Control architecture for ATM networks

Patents Applicationslast 30 patents

Resonant Clock Distribution Network Architecture for Tracking Param...

Architecture for Single-Stepping in Resonant Clock Distribution Net...

Architecture for Adjusting Natural Frequency in Resonant Clock Dist...

Method for Selecting Natural Frequency in Resonant Clock Distributi...

Resonant Clock And Interconnect Architecture For Digital Devices Wi...

RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE WITH PROGRAMMABLE...

ARCHITECTURE FOR ADJUSTING NATURAL FREQUENCY IN RESONANT CLOCK DIST...

ARCHITECTURE FOR FREQUENCY-SCALED OPERATION IN RESONANT CLOCK DISTR...

ARCHITECTURE FOR CONTROLLING CLOCK CHARACTERISTICS

METHOD FOR SELECTING NATURAL FREQUENCY IN RESONANT CLOCK DISTRIBUTI...

ARCHITECTURE FOR SINGLE-STEPPING IN RESONANT CLOCK DISTRIBUTION NET...

ARCHITECTURE FOR OPERATING RESONANT CLOCK NETWORK IN CONVENTIONAL MODE

RESONANT CLOCK DISTRIBUTION NETWORK ARCHITECTURE FOR TRACKING PARAM...

RESONANT CLOCK AND INTERCONNECT ARCHITECTURE FOR DIGITAL DEVICES WI...