Alexander Shubat

Person

Newark, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Detecting random telegraph noise induced failures in an electronic...
- Patent number 8,850,277
- Issue date Sep 30, 2014
- Synopsys, Inc.
- Karen Amirkhanyan
- G11 - INFORMATION STORAGE
Information Patent Grant
Various methods and apparatuses for memory modeling using a structu...
- Patent number 8,112,730
- Issue date Feb 7, 2012
- Synopsys, Inc.
- Karen Aleksanyan
- G11 - INFORMATION STORAGE
Information Patent Grant
Statistical yield of a system-on-a-chip
- Patent number 7,904,766
- Issue date Mar 8, 2011
- Synopsys, Inc.
- Niranjan Behera
Information Patent Grant
Source-biased SRAM cell with reduced memory cell leakage
- Patent number 7,692,964
- Issue date Apr 6, 2010
- Virage Logic Corp.
- Deepak Sabharwal
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for providing adjustable read margins in a semico...
- Patent number 7,458,005
- Issue date Nov 25, 2008
- Virage Logic Corp.
- Alex Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for compiling a memory assembly with redundancy i...
- Patent number 7,406,620
- Issue date Jul 29, 2008
- Virage Logic Corp.
- Alex Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for providing adjustable read margins in a semico...
- Patent number 7,114,118
- Issue date Sep 26, 2006
- Virage Logic Corp.
- Alex Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Embedded test and repair scheme and interface for compiling a memor...
- Patent number 7,093,156
- Issue date Aug 15, 2006
- Virage Logic Corp.
- Alex Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline-based source-biasing scheme for reducing memory cell leakage
- Patent number 7,061,794
- Issue date Jun 13, 2006
- Virage Logic Corp.
- Deepak Sabharwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses for a ROM memory array having a virtually g...
- Patent number 7,002,827
- Issue date Feb 21, 2006
- Virage Logic Corporation
- Deepak Sabharwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses for test circuitry for a dual-polarity non-...
- Patent number 6,992,938
- Issue date Jan 31, 2006
- Virage Logic Corporation
- Alexander Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Radiation-hardened static memory cell using isolation technology
- Patent number 6,744,661
- Issue date Jun 1, 2004
- Virage Logic Corp.
- Alex Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for memory characterization
- Patent number 6,738,953
- Issue date May 18, 2004
- Virage Logic Corp.
- Deepak Sabharwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to reduce the amount of redundant memory colum...
- Patent number 6,646,933
- Issue date Nov 11, 2003
- Virage Logic Corporation
- Alexander Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for redundancy implementation in a semiconductor...
- Patent number 6,556,490
- Issue date Apr 29, 2003
- Virage Logic Corp.
- Alex Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to change the amount of redundant memory colum...
- Patent number 6,519,202
- Issue date Feb 11, 2003
- Virage Logic Corporation
- Alexander Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast read/write cycle memory device having a self-timed read/write...
- Patent number 6,392,957
- Issue date May 21, 2002
- Virage Logic Corporation
- Alexander Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture with multi-instance redundancy implementation
- Patent number 6,363,020
- Issue date Mar 26, 2002
- Virage Logic Corp.
- Alex Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for testing multiple port memory devices
- Patent number 6,269,036
- Issue date Jul 31, 2001
- Virage Logic Corporation
- Alexander Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Module-based logic architecture and design flow for VLSI implementa...
- Patent number 6,051,031
- Issue date Apr 18, 2000
- Virage Logic Corporation
- Alexander Shubat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unit for stabilizing voltage on a capacitive node
- Patent number 5,568,085
- Issue date Oct 22, 1996
- WaferScale Integration Inc.
- Boaz Eitan
- G05 - CONTROLLING REGULATING
Information Patent Grant
MOS SRAM cell with open base bipolar loads
- Patent number 5,453,636
- Issue date Sep 26, 1995
- WaferScale Integration, Inc.
- Boaz Eitan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrically programmable read only memory array
- Patent number 5,432,730
- Issue date Jul 11, 1995
- WaferScale Integration, Inc.
- Alex Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Peripheral port with volatile and non-volatile configuration
- Patent number 5,402,014
- Issue date Mar 28, 1995
- WaferScale Integration, Inc.
- Arye Ziklik
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Page register with a don't care function
- Patent number 5,347,641
- Issue date Sep 13, 1994
- WaferScale Integration, Inc.
- Yoram Cedar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Glitch free power-up for a programmable array
- Patent number 5,136,186
- Issue date Aug 4, 1992
- WaferScale Integration, Incorporation
- Cuong Trinh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Decoder for a memory address bus
- Patent number 4,961,172
- Issue date Oct 2, 1990
- WaferScale Integration, Inc.
- Alexander Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Output circuit for driving a memory device output lead including a...
- Patent number 4,939,392
- Issue date Jul 3, 1990
- WaferScale Integration, Inc.
- Alexander Shubat
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC...
- Publication number 20130019132
- Publication date Jan 17, 2013
- Synopsys Inc.
- Karen AMIRKHANYAN
- G11 - INFORMATION STORAGE
Information Patent Application
VARIOUS METHODS AND APPARATUSES FOR MEMORY MODELING USING A STRUCTU...
- Publication number 20090106716
- Publication date Apr 23, 2009
- Virage Logic Corporation
- Karen Aleksanyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for compiling a memory assembly with redundancy i...
- Publication number 20060277430
- Publication date Dec 7, 2006
- Virage Logic Corp.
- Alex Shubat
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for redundancy implementation in a semiconductor...
- Publication number 20020154553
- Publication date Oct 24, 2002
- Alex Shubat
- G11 - INFORMATION STORAGE

Alexander Shubat

Person

Patents Grantslast 30 patents

Detecting random telegraph noise induced failures in an electronic...

Various methods and apparatuses for memory modeling using a structu...

Statistical yield of a system-on-a-chip

Source-biased SRAM cell with reduced memory cell leakage

System and method for providing adjustable read margins in a semico...

System and method for compiling a memory assembly with redundancy i...

System and method for providing adjustable read margins in a semico...

Embedded test and repair scheme and interface for compiling a memor...

Wordline-based source-biasing scheme for reducing memory cell leakage

Methods and apparatuses for a ROM memory array having a virtually g...

Methods and apparatuses for test circuitry for a dual-polarity non-...

Radiation-hardened static memory cell using isolation technology

System and method for memory characterization

Method and apparatus to reduce the amount of redundant memory colum...

System and method for redundancy implementation in a semiconductor...

Method and apparatus to change the amount of redundant memory colum...

Fast read/write cycle memory device having a self-timed read/write...

Architecture with multi-instance redundancy implementation

System and method for testing multiple port memory devices

Module-based logic architecture and design flow for VLSI implementa...

Unit for stabilizing voltage on a capacitive node

MOS SRAM cell with open base bipolar loads

Electrically programmable read only memory array

Peripheral port with volatile and non-volatile configuration

Page register with a don't care function

Glitch free power-up for a programmable array

Decoder for a memory address bus

Output circuit for driving a memory device output lead including a...

Patents Applicationslast 30 patents

DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC...

VARIOUS METHODS AND APPARATUSES FOR MEMORY MODELING USING A STRUCTU...

System and method for compiling a memory assembly with redundancy i...

System and method for redundancy implementation in a semiconductor...