Alexander Tessarolo

Person

Lindfield NSW, AU

People

Patents Grantslast 30 patents

Information Patent Grant
Instruction packing scheme for VLIW CPU architecture
- Patent number 11,593,110
- Issue date Feb 28, 2023
- Texas Instruments Incorporated
- Saya Goud Langadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and instruction set to support interruptible floating...
- Patent number 10,635,395
- Issue date Apr 28, 2020
- Texas Instruments Incorporated
- Prasanth Viswanathan Pillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and instruction set to support integer division
- Patent number 10,628,126
- Issue date Apr 21, 2020
- Texas Instruments Incorporated
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and instruction set to support integer division
- Patent number 10,359,995
- Issue date Jul 23, 2019
- Texas Instruments Incorporated
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High resolution capture
- Patent number 10,177,747
- Issue date Jan 8, 2019
- Texas Instruments Incorporated
- Alexander Tessarolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interruptible trigonometric operations
- Patent number 10,168,992
- Issue date Jan 1, 2019
- Texas Instruments Incorporated
- Prasanth Viswanathan Pillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to perform serial communications
- Patent number 9,614,704
- Issue date Apr 4, 2017
- Texas Instruments Incorporated
- Venkatesh Natarajan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Approach for significant improvement of FFT performance in microcon...
- Patent number 9,311,274
- Issue date Apr 12, 2016
- Texas Instruments Incorporated
- Prohor Chowdhury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Viterbi butterfly operations
- Patent number 8,943,392
- Issue date Jan 27, 2015
- Texas Instruments Incorporated
- Prohor Chowdhury
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Co-hosted cyclical redundancy check calculation
- Patent number 8,739,012
- Issue date May 27, 2014
- Texas Instruments Incorporated
- Prohor Chowdhury
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Processor instructions to accelerate Viterbi decoding
- Patent number 8,694,878
- Issue date Apr 8, 2014
- Texas Instruments Incorporated
- Prohor Chowdhury
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Microcontroller with secure feature for multiple party code develop...
- Patent number 8,539,602
- Issue date Sep 17, 2013
- Texas Instruments Incorporated
- Prohor Chowdhury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for control with a multi-chip module with multi...
- Patent number 8,538,558
- Issue date Sep 17, 2013
- Texas Instruments Incorporated
- Sam Gnana Sabapathy
- G05 - CONTROLLING REGULATING
Information Patent Grant
High resolution capture
- Patent number 8,384,440
- Issue date Feb 26, 2013
- Texas Instruments Incorporated
- Alexander Tessarolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Processor with summation instruction using overflow counter
- Patent number 7,590,677
- Issue date Sep 15, 2009
- Texas Instruments Incorporated
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with maximum and minimum instructions
- Patent number 7,580,967
- Issue date Aug 25, 2009
- Texas Instruments Incorporated
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with scaled sum-of-product instructions
- Patent number 7,580,968
- Issue date Aug 25, 2009
- Texas Instruments Incorporated
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for test, characterization, and calibration of...
- Patent number 7,495,429
- Issue date Feb 24, 2009
- Texas Instruments Incorporated
- Alexander Tessarolo
- G01 - MEASURING TESTING
Information Patent Grant
Speed of execution of a conditional subtract instruction and increa...
- Patent number 7,237,000
- Issue date Jun 26, 2007
- Texas Instruments Incorporated
- Ajit Gupte
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circular addressing algorithms providing increased compatibility wi...
- Patent number 7,039,789
- Issue date May 2, 2006
- Texas Instruments Incorporated
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Repeat block with zero cycle overhead nesting
- Patent number 6,986,028
- Issue date Jan 10, 2006
- Texas Instruments Incorporated
- Peter N. Ehlig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital signal processing unit with emulation circuitry and debug i...
- Patent number 6,567,910
- Issue date May 20, 2003
- Texas Instruments Incorporated
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for manipulating data for aligning the stack m...
- Patent number 6,341,344
- Issue date Jan 22, 2002
- Texas Instruments Incorporated
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for extending register dynamic range
- Patent number 6,243,731
- Issue date Jun 5, 2001
- Texas Instruments Incorporated
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Reducing Overhead In Processor Array Searching
- Publication number 20240111541
- Publication date Apr 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- ALAN DAVIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURING REGISTERS ACROSS SECURITY ZONES
- Publication number 20240069920
- Publication date Feb 29, 2024
- TEXAS INSTRUMENTS INCORPORATED
- David P. FOLEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION PACKING SCHEME FOR VLIW CPU ARCHITECTURE
- Publication number 20230221959
- Publication date Jul 13, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Saya Goud Langadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION PACKING SCHEME FOR VLIW CPU ARCHITECTURE
- Publication number 20220214880
- Publication date Jul 7, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Saya Goud Langadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE AND INSTRUCTION SET TO SUPPORT INTEGER DIVISION
- Publication number 20190286418
- Publication date Sep 19, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Alexander TESSAROLO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE AND INSTRUCTION SET TO SUPPORT INTERRUPTIBLE FLOATING...
- Publication number 20180004485
- Publication date Jan 4, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Prasanth VISWANATHAN PILLAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE AND INSTRUCTION SET TO SUPPORT INTEGER DIVISION
- Publication number 20170315779
- Publication date Nov 2, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Alexander TESSAROLO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Resolution Capture
- Publication number 20170149418
- Publication date May 25, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Alexander Tessarolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND APPARATUS TO PERFORM SERIAL COMMUNICATIONS
- Publication number 20170033955
- Publication date Feb 2, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Venkatesh Natarajan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
NOVEL APPROACH FOR SIGNIFICANT IMPROVEMENT OF FFT PERFORMANCE IN MI...
- Publication number 20150113030
- Publication date Apr 23, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Prohor CHOWDHURY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR FOR SOLVING MATHEMATICAL OPERATIONS
- Publication number 20140324936
- Publication date Oct 30, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Tessarolo Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VITERBI BUTTERFLY OPERATIONS
- Publication number 20140129908
- Publication date May 8, 2014
- Texas Instruments, Incorporated
- Prohor Chowdhury
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR CONTROL WITH A MULTI-CHIP MODULE WITH MULTI...
- Publication number 20130231767
- Publication date Sep 5, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Sam Gnana Sabapathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Microcontroller with Secure Feature for Multiple Party Code Develop...
- Publication number 20120331560
- Publication date Dec 27, 2012
- Prohor Chowdhury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH RESOLUTION CAPTURE
- Publication number 20120319751
- Publication date Dec 20, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Alexander Tessarolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Processor Instructions to Accelerate Viterbi Decoding
- Publication number 20120324318
- Publication date Dec 20, 2012
- Prohor Chowdhury
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CO-HOSTED CYCLICAL REDUNDANCY CHECK CALCULATION
- Publication number 20120324321
- Publication date Dec 20, 2012
- Texas Instruments, Incorporated
- Prohor Chowdhury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus And Method For Test, Characterization, And Calibration Of...
- Publication number 20090167317
- Publication date Jul 2, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Alexander Tessarolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and method for test, characterization, and calibration of...
- Publication number 20060156150
- Publication date Jul 13, 2006
- Alexander Tessarolo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and method for synchronized distributed pulse width modul...
- Publication number 20050242858
- Publication date Nov 3, 2005
- David A. Figoli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Repeat block with zero cycle overhead nesting
- Publication number 20030200423
- Publication date Oct 23, 2003
- Peter N. Ehlig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Atomically testing and setting or clearing one or more bits stored...
- Publication number 20030172238
- Publication date Sep 11, 2003
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circular addressing algorithms providing increased compatibility wi...
- Publication number 20030172246
- Publication date Sep 11, 2003
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Calculating a sum of numbers using an overflow counter in an enviro...
- Publication number 20030172100
- Publication date Sep 11, 2003
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Limiting the valve of a 64-bit number to a maximum value, a minimum...
- Publication number 20030163499
- Publication date Aug 28, 2003
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
64-bit scaled sum-of-product operations in a 32-bit environment
- Publication number 20030163500
- Publication date Aug 28, 2003
- Alexander Tessarolo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Speed of execution of a conditional subtract instruction and increa...
- Publication number 20030037088
- Publication date Feb 20, 2003
- TEXAS INSTRUMENTS INCORPORATED
- Ajit Gupte
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR CODE-ENHANCED PERFORMANCE IN A DIGITAL SIG...
- Publication number 20020112144
- Publication date Aug 15, 2002
- ALEXANDER TESSAROLO
- G06 - COMPUTING CALCULATING COUNTING

Alexander Tessarolo

Person

Patents Grantslast 30 patents

Instruction packing scheme for VLIW CPU architecture

Architecture and instruction set to support interruptible floating...

Architecture and instruction set to support integer division

Architecture and instruction set to support integer division

High resolution capture

Interruptible trigonometric operations

Methods and apparatus to perform serial communications

Approach for significant improvement of FFT performance in microcon...

Viterbi butterfly operations

Co-hosted cyclical redundancy check calculation

Processor instructions to accelerate Viterbi decoding

Microcontroller with secure feature for multiple party code develop...

Systems and methods for control with a multi-chip module with multi...

High resolution capture

Processor with summation instruction using overflow counter

Processor with maximum and minimum instructions

Processor with scaled sum-of-product instructions

Apparatus and method for test, characterization, and calibration of...

Speed of execution of a conditional subtract instruction and increa...

Circular addressing algorithms providing increased compatibility wi...

Repeat block with zero cycle overhead nesting

Digital signal processing unit with emulation circuitry and debug i...

Apparatus and method for manipulating data for aligning the stack m...

Apparatus and method for extending register dynamic range

Patents Applicationslast 30 patents

Reducing Overhead In Processor Array Searching

SECURING REGISTERS ACROSS SECURITY ZONES

INSTRUCTION PACKING SCHEME FOR VLIW CPU ARCHITECTURE

INSTRUCTION PACKING SCHEME FOR VLIW CPU ARCHITECTURE

ARCHITECTURE AND INSTRUCTION SET TO SUPPORT INTEGER DIVISION

ARCHITECTURE AND INSTRUCTION SET TO SUPPORT INTERRUPTIBLE FLOATING...

ARCHITECTURE AND INSTRUCTION SET TO SUPPORT INTEGER DIVISION

High Resolution Capture

METHODS AND APPARATUS TO PERFORM SERIAL COMMUNICATIONS

NOVEL APPROACH FOR SIGNIFICANT IMPROVEMENT OF FFT PERFORMANCE IN MI...

PROCESSOR FOR SOLVING MATHEMATICAL OPERATIONS

VITERBI BUTTERFLY OPERATIONS

SYSTEMS AND METHODS FOR CONTROL WITH A MULTI-CHIP MODULE WITH MULTI...

Microcontroller with Secure Feature for Multiple Party Code Develop...

HIGH RESOLUTION CAPTURE

Processor Instructions to Accelerate Viterbi Decoding

CO-HOSTED CYCLICAL REDUNDANCY CHECK CALCULATION

Apparatus And Method For Test, Characterization, And Calibration Of...

Apparatus and method for test, characterization, and calibration of...

Apparatus and method for synchronized distributed pulse width modul...

Repeat block with zero cycle overhead nesting

Atomically testing and setting or clearing one or more bits stored...

Circular addressing algorithms providing increased compatibility wi...

Calculating a sum of numbers using an overflow counter in an enviro...

Limiting the valve of a 64-bit number to a maximum value, a minimum...

64-bit scaled sum-of-product operations in a 32-bit environment

Speed of execution of a conditional subtract instruction and increa...

APPARATUS AND METHOD FOR CODE-ENHANCED PERFORMANCE IN A DIGITAL SIG...