Alexandre Andreev

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for generating memory models and timing database
- Patent number 8,566,769
- Issue date Oct 22, 2013
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Universal Galois field multiplier
- Patent number 8,312,072
- Issue date Nov 13, 2012
- LSI Corporation
- Sergei B. Gashkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating memory models and timing database
- Patent number 8,245,168
- Issue date Aug 14, 2012
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reed-solomon decoder with a variable number of correctable errors
- Patent number 8,209,589
- Issue date Jun 26, 2012
- LSI Corporation
- Alexandre Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable redundancy reed-solomon encoder
- Patent number 8,176,397
- Issue date May 8, 2012
- LSI Corporation
- Pavel Panteleev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data controlling in the MBIST chain architecture
- Patent number 8,156,391
- Issue date Apr 10, 2012
- LSI Corporation
- Alexandre Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Transport subsystem for an MBIST chain architecture
- Patent number 8,046,643
- Issue date Oct 25, 2011
- LSI Corporation
- Alexandre Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for mapping design memories to integrated circ...
- Patent number 8,037,432
- Issue date Oct 11, 2011
- LSI Corporation
- Alexandre Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Address controlling in the MBIST chain architecture
- Patent number 7,949,909
- Issue date May 24, 2011
- LSI Corporation
- Alexandre Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Generation of test sequences during memory built-in self testing of...
- Patent number 7,788,563
- Issue date Aug 31, 2010
- LSI Corporation
- Alexandre E. Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for generating memory models and timing database
- Patent number 7,584,442
- Issue date Sep 1, 2009
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for mapping design memories to integrated circ...
- Patent number 7,424,687
- Issue date Sep 9, 2008
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for tiling memories in integrated circuit layout
- Patent number 7,389,484
- Issue date Jun 17, 2008
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Master controller architecture
- Patent number 7,308,633
- Issue date Dec 11, 2007
- LSI Corporation
- Alexandre Andreev
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory tiling architecture
- Patent number 7,207,026
- Issue date Apr 17, 2007
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RRAM memory timing learning tool
- Patent number 7,200,826
- Issue date Apr 3, 2007
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory generation and placement
- Patent number 7,155,688
- Issue date Dec 26, 2006
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for classifying an integrated circuit for optical...
- Patent number 7,093,228
- Issue date Aug 15, 2006
- LSI Logic Corporation
- Alexandre Andreev
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Multidirectional router
- Patent number 6,845,495
- Issue date Jan 18, 2005
- LSI Logic Corporation
- Alexandre E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power routing with obstacles
- Patent number 6,757,881
- Issue date Jun 29, 2004
- LSI Logic Corporation
- Alexandre E. Andreev
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for Generating Memory Models and Timing Database
- Publication number 20120278775
- Publication date Nov 1, 2012
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE REDUNDANCY REED-SOLOMON ENCODER
- Publication number 20100070831
- Publication date Mar 18, 2010
- Elyar Gasanov
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
UNIVERSAL GALOIS FIELD MULTIPLIER
- Publication number 20100070548
- Publication date Mar 18, 2010
- Sergei B. Gashkov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REED-SOLOMON DECODER WITH A VARIABLE NUMBER OF CORRECTABLE ERRORS
- Publication number 20100070832
- Publication date Mar 18, 2010
- Alexandre Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and Apparatus for Generating Memory Models and Timing Database
- Publication number 20100023904
- Publication date Jan 28, 2010
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generation Of Test Sequences During Memory Built-In Self Testing Of...
- Publication number 20090316507
- Publication date Dec 24, 2009
- Alexandre E. Andreev
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSPORT SUBSYSTEM FOR AN MBIST CHAIN ARCHITECTURE
- Publication number 20090307543
- Publication date Dec 10, 2009
- Alexandre Andreev
- G11 - INFORMATION STORAGE
Information Patent Application
DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE
- Publication number 20090300440
- Publication date Dec 3, 2009
- Alexandre Andreev
- G11 - INFORMATION STORAGE
Information Patent Application
ADDRESS CONTROLLING IN THE MBIST CHAIN ARCHITECTURE
- Publication number 20090300441
- Publication date Dec 3, 2009
- Alexandre Andreev
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT IN TEST CONTROLLER WITH A DOWNLOADABLE TESTING PROGRAM
- Publication number 20090282303
- Publication date Nov 12, 2009
- Alexandre Andreev
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRC...
- Publication number 20080295044
- Publication date Nov 27, 2008
- LSI Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for generating memory models and timing database
- Publication number 20070136704
- Publication date Jun 14, 2007
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for tiling memories in integrated circuit layout
- Publication number 20070108961
- Publication date May 17, 2007
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for mapping design memories to integrated circ...
- Publication number 20070113212
- Publication date May 17, 2007
- LSI Logic Corporation
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Master controller architecture
- Publication number 20060129874
- Publication date Jun 15, 2006
- Alexandre Andreev
- G11 - INFORMATION STORAGE
Information Patent Application
RRAM memory timing learning tool
- Publication number 20060117284
- Publication date Jun 1, 2006
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory generation and placement
- Publication number 20060107247
- Publication date May 18, 2006
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory tiling architecture
- Publication number 20060104145
- Publication date May 18, 2006
- Alexandre Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for generating tech-library for logic function
- Publication number 20040221247
- Publication date Nov 4, 2004
- Alexandre E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for classifying an integrated circut for optical...
- Publication number 20040123265
- Publication date Jun 24, 2004
- Alexandre Andreev
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Power routing with obstacles
- Publication number 20030145302
- Publication date Jul 31, 2003
- Alexandre E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multidirectional router
- Publication number 20030121017
- Publication date Jun 26, 2003
- Alexandre E. Andreev
- G06 - COMPUTING CALCULATING COUNTING

Alexandre Andreev

Person

Patents Grantslast 30 patents

Method and apparatus for generating memory models and timing database

Universal Galois field multiplier

Method and apparatus for generating memory models and timing database

Reed-solomon decoder with a variable number of correctable errors

Variable redundancy reed-solomon encoder

Data controlling in the MBIST chain architecture

Transport subsystem for an MBIST chain architecture

Method and apparatus for mapping design memories to integrated circ...

Address controlling in the MBIST chain architecture

Generation of test sequences during memory built-in self testing of...

Method and apparatus for generating memory models and timing database

Method and apparatus for mapping design memories to integrated circ...

Method and apparatus for tiling memories in integrated circuit layout

Master controller architecture

Memory tiling architecture

RRAM memory timing learning tool

Memory generation and placement

Method and system for classifying an integrated circuit for optical...

Multidirectional router

Power routing with obstacles

Patents Applicationslast 30 patents

Method and Apparatus for Generating Memory Models and Timing Database

VARIABLE REDUNDANCY REED-SOLOMON ENCODER

UNIVERSAL GALOIS FIELD MULTIPLIER

REED-SOLOMON DECODER WITH A VARIABLE NUMBER OF CORRECTABLE ERRORS

Method and Apparatus for Generating Memory Models and Timing Database

Generation Of Test Sequences During Memory Built-In Self Testing Of...

TRANSPORT SUBSYSTEM FOR AN MBIST CHAIN ARCHITECTURE

DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE

ADDRESS CONTROLLING IN THE MBIST CHAIN ARCHITECTURE

BUILT IN TEST CONTROLLER WITH A DOWNLOADABLE TESTING PROGRAM

METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRC...

Method and apparatus for generating memory models and timing database

Method and apparatus for tiling memories in integrated circuit layout

Method and apparatus for mapping design memories to integrated circ...

Master controller architecture

RRAM memory timing learning tool

Memory generation and placement

Memory tiling architecture

Method for generating tech-library for logic function

Method and system for classifying an integrated circut for optical...

Power routing with obstacles

Multidirectional router