Claims
- 1. A method for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design, the method comprising the steps of:
(a) dividing the IC chip into a plurality of local task regions; (b) identifying congruent local task regions; (c) classifying congruent local task regions into corresponding groups; and (d) performing OPC for each group of congruent local task regions.
- 2. The method of claim 1, wherein identifying step (b) further includes:
(b1) generating a characteristic vector for each local task region.
- 3. The method of claim 2, wherein identifying step (b) further includes:
(b2) comparing the characteristic vectors to determine congruent local task regions.
- 4. The method of claim 2, wherein identifying step (b) further includes:
(b2) normalizing each of the characteristic vectors.
- 5. The method of claim 4, wherein the identifying step (b) further includes:
(b3) comparing the normalized characteristic vectors to determine congruent local task regions.
- 6. The method of claim 4, wherein the identifying step (b) further includes:
(b3) hashing each of the normalized characteristic vectors to produce a corresponding hash value; (b4) comparing the corresponding hash values; and (b5) subclassifying the hash values by the corresponding characteristic vectors.
- 7. The method of claim 4, wherein generating step (b1) further includes:
b1i) providing a plurality of feature types used in the IC chip design, wherein each feature type is assigned an index; and b1ii) for each local task region, generating a characteristic vector based on one or more feature types intersecting an extended task region for the local task region, wherein the extended task region comprises the local task region and an area surrounding the local task region corresponding to an area of optical influence.
- 8. The method of claim 7, wherein the characteristic vector for a local task region describes each intersecting feature type and its orientation and position relative to an origin point at a center of the local task region.
- 9. The method of claim 7, wherein the normalizing step (b2) further includes the steps of:
(b2i) sorting the characteristic vector by increasing feature type index; and (b2ii) manipulating the local task region to place a first feature type in a original orientation.
- 10. The method of claim 1, wherein the dividing step (a) includes:
(a1) providing a plurality of square local task regions, wherein a size of each of the local task regions is a multiple of a layout grid size of the IC chip.
- 11. The method of claim 1, further including the step of:
(e) generating a list of different local task regions to be corrected; and (f) submitting the list to an OPC engine for correction.
- 12. The method of claim 7, wherein the generating step (b1ii) further includes:
(b1ii(a)) initializing each characteristic vector to zero value; (b1ii(b)) traversing a IC chip design hierarchy to identify a first feature type instance; (b1ii(c)) determining an absolute location on a layout grid of the identified feature type instance; (b1ii(d)) identifying one or more extended task regions intersecting the identified feature type instance, wherein an extended task region comprises the local task region and an area surrounding the local task region corresponding to an area of optical influence; (b1ii(e)) updating the characteristic vectors corresponding to the local task regions associated with the extended task regions identified in step (b1iid) to describe identified feature type instance; (b1ii(f)) traversing the IC chip design hierarchy to identify a next feature type instance; and (b1ii(g)) repeating steps (b1ii(c)) through (b1ii(f)) until all feature type instances have been identified.
- 13. A computer based system for performing optical proximity correction on an integrated circuit (“IC”) chip design comprising:
a storage device; a classification module coupled to the storage device for dividing the IC chip design into a plurality of local task regions, identifying congruent local task regions, and classifying congruent local task regions into corresponding groups; and an optical proximity correction module coupled to the classification module for performing optical proximity correction for each group of congruent local task regions.
- 14. The system of claim 11, wherein a plurality of feature types used in the IC chip design are stored in the storage device and wherein each feature type is assigned an index.
- 15. The system of claim 12, wherein the classification module further generates, for each local task region, a characteristic vector based on one or more feature types intersecting an extended task region for the local task region, wherein the extended task region comprises the local task region and an area of optical influence.
- 16. The system of claim 13, wherein the classification module further normalizes each of the characteristic vectors.
- 17. The system of claim 16 further including a hashing unit coupled to the classification module for hashing each of the normalized characteristic vectors to produce a corresponding hash value, wherein the classification module compares the corresponding hash values and subclassifies the hash values by the corresponding characteristic vectors.
- 18. The system of claim 12, wherein the classification module further generates a list of different local task regions to be corrected and submits the list to the optical proximity correction module for correction.
- 19. A computer readable medium containing programming instructions for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design, the programming instructions for:
(a) dividing the IC chip into a plurality of local task regions; (b) identifying congruent local task regions; (c) classifying congruent local task regions into corresponding groups; and (d) performing OPC for each group of congruent local task regions.
- 20. The computer readable medium of claim 19, wherein identifying instruction (b) further includes:
(b1) generating a characteristic vector for each local task region.
- 21. The computer readable medium of claim 20, wherein identifying step (b) further includes:
(b2) comparing the characteristic vectors to determine congruent local task regions.
- 22. The computer readable medium of claim 20, wherein identifying step (b) further includes:
(b2) normalizing each of the characteristic vectors.
- 23. The computer readable medium of claim 22, wherein the identifying step (b) further includes:
(b3) comparing the normalized characteristic vectors to determine congruent local task regions.
- 24. The computer readable medium of claim 22, wherein the identifying step (b) further includes:
(b3) hashing each of the normalized characteristic vectors to produce a corresponding hash value; (b4) comparing the corresponding hash values; and (b5) subclassifying the hash values by the corresponding characteristic vectors.
- 25. The computer readable medium of claim 22, wherein generating step (b1) further includes:
b1i) providing a plurality of feature types used in the IC chip design, wherein each feature type is assigned an index; and b1ii) for each local task region, generating a characteristic vector based on one or more feature types intersecting an extended task region for the local task region, wherein the extended task region comprises the local task region and an area surrounding the local task region corresponding to an area of optical influence.
- 26. The computer readable medium of claim 25, wherein the characteristic vector for a local task region describes each intersecting feature type and its orientation and position relative to an origin point at a center of the local task region.
- 27. The computer readable medium of claim 25, wherein the normalizing step (b2) further includes the steps of:
(b2i) sorting the characteristic vector by increasing feature type index; and (b2ii) manipulating the local task region to place a first feature type in a predetermined original orientation.
- 28. The computer readable medium of claim 19, wherein the dividing (a) includes:
(a1) providing a plurality of square local task regions, wherein a size of each of the local task regions is a multiple of a layout grid size of the IC chip.
- 29. The computer readable medium of claim 19, further including the instruction for:
(e) generating a list of different local task regions to be corrected; and (f) submitting the list to an OPC engine for correction.
- 30. The computer readable medium of claim 25, wherein the generating instruction (b1ii) further includes:
initializing each characteristic vector to zero value; traversing a IC chip design hierarchy to identify a first feature type instance; determining an absolute location on a layout grid of the identified feature type instance; identifying one or more extended task regions intersecting the identified feature type instance; updating the characteristic vectors corresponding to the local task regions associated with the extended task regions identified in the previous step to describe the identified feature type instance; traversing the IC chip design hierarchy to identify a next feature type instance; and repeating the above steps until all feature type instances have been identified.
- 31. A method for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design, the method comprising the steps of:
(a) dividing the IC chip into a plurality of local task regions; (b) for each local task region, generating a characteristic vector based on one or more feature types intersecting an extended task region for the local task region, wherein the extended task region comprises the local task region and an area surrounding the local task region corresponding to an area of optical influence; (c) normalizing each of the characteristic vectors; (d) hashing each of the normalized characteristic vectors to produce a corresponding hash value; (e) sorting the corresponding hash values; (f) subclassifying the hash values by the corresponding characteristic vectors; and (g) performing OPC for each group of characteristic vectors corresponding to congruent local task regions.
- 32. The method of claim 31, wherein hashing step (d) further includes:
(d1) selecting a first and a second random regular bit matrix, wherein the first and the second matrices are of size N X N; (d2) dividing each characteristic vector into m groups of N sized bit vectors; and (d3) calculating a hash value for each characteristic vector by iteratively multiplying a first group of m bit vectors with the first matrix and adding the second matrix.
- 33. The method of claim 32, wherein N is 32.
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is related to co-pending patent application Ser. No. ______, entitled “Method and System for Hierarchy Driven Chip Covering for OPC Purposes,” filed on the same day and assigned to the same Assignee as the present application.