Amit Sanghani

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Test architecture for die to die interconnect for three dimensional...
- Patent number 11,257,560
- Issue date Feb 22, 2022
- Intel Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Grant
Granular dynamic test systems and methods
- Patent number 10,481,203
- Issue date Nov 19, 2019
- NVIDIA Corporation
- Shantanu Sarangi
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic independent test partition clock
- Patent number 10,473,720
- Issue date Nov 12, 2019
- NVIDIA Corporation
- Pavan Kumar Datla Jagannadha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Independent test partition clock coordination across multiple test...
- Patent number 10,444,280
- Issue date Oct 15, 2019
- NVIDIA Corporation
- Dheepakkumaran Jayaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan system interface (SSI) module
- Patent number 10,317,463
- Issue date Jun 11, 2019
- NVIDIA Corporation
- Milind Sonawane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test partition external input/output interface control for test par...
- Patent number 10,281,524
- Issue date May 7, 2019
- NVIDIA Corporation
- Sailendra Chadalavda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual access of input/output (I/O) for test via an on-chip star n...
- Patent number 10,241,148
- Issue date Mar 26, 2019
- NVIDIA Corporation
- Ashfaq Shaikh
- G01 - MEASURING TESTING
Information Patent Grant
Scan systems and methods
- Patent number 9,885,753
- Issue date Feb 6, 2018
- NVIDIA Corporation
- Amit Sanghani
- G01 - MEASURING TESTING
Information Patent Grant
Performing on-chip partial good die identification
- Patent number 9,829,536
- Issue date Nov 28, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Grant
Hybrid on-chip clock controller techniques for facilitating at-spee...
- Patent number 9,500,706
- Issue date Nov 22, 2016
- NVIDIA Corporation
- Amit Sanghani
- G01 - MEASURING TESTING
Information Patent Grant
System for reducing peak power during scan shift at the local level...
- Patent number 9,395,414
- Issue date Jul 19, 2016
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Grant
System for reducing peak power during scan shift at the global leve...
- Patent number 9,377,510
- Issue date Jun 28, 2016
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Grant
Global low power capture scheme for cores
- Patent number 9,222,981
- Issue date Dec 29, 2015
- NVIDIA Corporation
- Satya Puvvada
- G01 - MEASURING TESTING
Information Patent Grant
Simulating scan tests with reduced resources
- Patent number 8,943,457
- Issue date Jan 27, 2015
- NVIDIA Corporation
- Amit Dinesh Sanghani
- G01 - MEASURING TESTING
Information Patent Grant
Power droop reduction via clock-gating for at-speed scan testing
- Patent number 8,522,190
- Issue date Aug 27, 2013
- NVIDIA Corporation
- Amit Sanghani
- G01 - MEASURING TESTING
Information Patent Grant
Test clock generation for higher-speed testing of a semiconductor d...
- Patent number 7,305,598
- Issue date Dec 4, 2007
- Amit Sanghani
- G01 - MEASURING TESTING
Information Patent Grant
Built-in self-testing for double data rate input/output
- Patent number 6,816,991
- Issue date Nov 9, 2004
- Sun Microsystems, Inc.
- Amit Dinesh Sanghani
- G11 - INFORMATION STORAGE
Information Patent Grant
LSSD interface
- Patent number 6,629,277
- Issue date Sep 30, 2003
- Sun Microsystems, Inc.
- Amit D. Sanghani
- G01 - MEASURING TESTING
Information Patent Grant
Reinstate apparatus and method to recreate data background for test...
- Patent number 6,629,275
- Issue date Sep 30, 2003
- Sun Microsystems, Inc.
- Rahesh Y Pendurkar
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic test pattern generation modeling for LSSD to interface wi...
- Patent number 6,477,684
- Issue date Nov 5, 2002
- Sun Microsystems, Inc.
- Amit D. Sanghani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for scan test of SRAM for microprocessors having full sca...
- Patent number 6,047,386
- Issue date Apr 4, 2000
- Sun Microsystems, Inc.
- Amit D. Sanghani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for scan test of SRAM for microprocessor witho...
- Patent number 6,014,762
- Issue date Jan 11, 2000
- Sun Microsystems, Inc.
- Amit D. Sanghani
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for scan test of SRAM for microprocessors having full scan c...
- Patent number 5,923,835
- Issue date Jul 13, 1999
- Sun Microsystems, Inc.
- Amit D. Sanghani
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for scan test of SRAM for microprocessors with...
- Patent number 5,896,396
- Issue date Apr 20, 1999
- Sun Microsystems, Inc.
- Amit D. Sanghani
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for scan test of SRAM for microprocessors having full sca...
- Patent number 5,881,218
- Issue date Mar 9, 1999
- Sun Microsystems, Inc.
- Amit D. Sanghani
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DESIGN FOR TEST ARCHITECTURE FOR DIE TO DIE INTERCONNECT FOR THREE...
- Publication number 20190096503
- Publication date Mar 28, 2019
- Intel Corporation
- Sreejit CHAKRAVARTY
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PERFORMING ON-CHIP PARTIAL GOOD DIE IDENTIFICATION
- Publication number 20170219652
- Publication date Aug 3, 2017
- NVIDIA Corporation
- Milind SONAWANE
- G01 - MEASURING TESTING
Information Patent Application
GRANULAR DYNAMIC TEST SYSTEMS AND METHODS
- Publication number 20170205465
- Publication date Jul 20, 2017
- NVIDIA Corporation
- Shantanu SARANGI
- G01 - MEASURING TESTING
Information Patent Application
TEST PARTITION EXTERNAL INPUT/OUTPUT INTERFACE CONTROL
- Publication number 20170115338
- Publication date Apr 27, 2017
- Sailendra Chadalavda
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC INDEPENDENT TEST PARTITION CLOCK
- Publication number 20170115351
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Pavan Kumar Datla Jagannadha
- G01 - MEASURING TESTING
Information Patent Application
GRANULAR DYNAMIC TEST SYSTEMS AND METHODS
- Publication number 20170115353
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
SCAN SYSTEM INTERFACE (SSI) MODULE
- Publication number 20170115346
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR DYNAMIC STANDARD TEST ACCESS (DSTA) FOR A LOG...
- Publication number 20170115345
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
INDEPENDENT TEST PARTITION CLOCK COORDINATION ACROSS MULTIPLE TEST...
- Publication number 20170115352
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Dheepakkumaran Jayaraman
- G01 - MEASURING TESTING
Information Patent Application
VIRTUAL ACCESS OF INPUT/OUTPUT (I/O) FOR TEST VIA AN ON-CHIP STAR N...
- Publication number 20170045575
- Publication date Feb 16, 2017
- NVIDIA Corporation
- Ashfaq SHAIKH
- G01 - MEASURING TESTING
Information Patent Application
HYBRID ON-CHIP CLOCK CONTROLLER TECHNIQUES FOR FACILITATING AT-SPEE...
- Publication number 20150204945
- Publication date Jul 23, 2015
- NVIDIA Corporation
- Amit SANGHANI
- G01 - MEASURING TESTING
Information Patent Application
SCAN SYSTEMS AND METHODS
- Publication number 20150100840
- Publication date Apr 9, 2015
- NVIDIA Corporation
- Amit SANGHANI
- G01 - MEASURING TESTING
Information Patent Application
GLOBAL LOW POWER CAPTURE SCHEME FOR CORES
- Publication number 20140189454
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Satya Puvvada
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM FOR REDUCING PEAK POWER DURING SCAN SHIFT AT THE GLOBAL LEVE...
- Publication number 20140189455
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM FOR REDUCING PEAK POWER DURING SCAN SHIFT AT THE LOCAL LEVEL...
- Publication number 20140189452
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
POWER DROOP REDUCTION VIA CLOCK-GATING FOR AT-SPEED SCAN TESTING
- Publication number 20130271197
- Publication date Oct 17, 2013
- Amit SANGHANI
- G01 - MEASURING TESTING
Information Patent Application
Simulating Scan Tests with Reduced Resources
- Publication number 20100131910
- Publication date May 27, 2010
- NVIDIA Corporation
- Amit Dinesh Sanghani
- G01 - MEASURING TESTING
Information Patent Application
Built-in self-testing for double data rate input/output
- Publication number 20030101376
- Publication date May 29, 2003
- Amit Dinesh Sanghani
- G01 - MEASURING TESTING

Amit Sanghani

Person

Patents Grantslast 30 patents

Test architecture for die to die interconnect for three dimensional...

Granular dynamic test systems and methods

Dynamic independent test partition clock

Independent test partition clock coordination across multiple test...

Scan system interface (SSI) module

Test partition external input/output interface control for test par...

Virtual access of input/output (I/O) for test via an on-chip star n...

Scan systems and methods

Performing on-chip partial good die identification

Hybrid on-chip clock controller techniques for facilitating at-spee...

System for reducing peak power during scan shift at the local level...

System for reducing peak power during scan shift at the global leve...

Global low power capture scheme for cores

Simulating scan tests with reduced resources

Power droop reduction via clock-gating for at-speed scan testing

Test clock generation for higher-speed testing of a semiconductor d...

Built-in self-testing for double data rate input/output

LSSD interface

Reinstate apparatus and method to recreate data background for test...

Automatic test pattern generation modeling for LSSD to interface wi...

Apparatus for scan test of SRAM for microprocessors having full sca...

Method and apparatus for scan test of SRAM for microprocessor witho...

Method for scan test of SRAM for microprocessors having full scan c...

Method and apparatus for scan test of SRAM for microprocessors with...

Apparatus for scan test of SRAM for microprocessors having full sca...

Patents Applicationslast 30 patents

DESIGN FOR TEST ARCHITECTURE FOR DIE TO DIE INTERCONNECT FOR THREE...

PERFORMING ON-CHIP PARTIAL GOOD DIE IDENTIFICATION

GRANULAR DYNAMIC TEST SYSTEMS AND METHODS

TEST PARTITION EXTERNAL INPUT/OUTPUT INTERFACE CONTROL

DYNAMIC INDEPENDENT TEST PARTITION CLOCK

GRANULAR DYNAMIC TEST SYSTEMS AND METHODS

SCAN SYSTEM INTERFACE (SSI) MODULE

METHOD AND SYSTEM FOR DYNAMIC STANDARD TEST ACCESS (DSTA) FOR A LOG...

INDEPENDENT TEST PARTITION CLOCK COORDINATION ACROSS MULTIPLE TEST...

VIRTUAL ACCESS OF INPUT/OUTPUT (I/O) FOR TEST VIA AN ON-CHIP STAR N...

HYBRID ON-CHIP CLOCK CONTROLLER TECHNIQUES FOR FACILITATING AT-SPEE...

SCAN SYSTEMS AND METHODS

GLOBAL LOW POWER CAPTURE SCHEME FOR CORES

SYSTEM FOR REDUCING PEAK POWER DURING SCAN SHIFT AT THE GLOBAL LEVE...

SYSTEM FOR REDUCING PEAK POWER DURING SCAN SHIFT AT THE LOCAL LEVEL...

POWER DROOP REDUCTION VIA CLOCK-GATING FOR AT-SPEED SCAN TESTING

Simulating Scan Tests with Reduced Resources

Built-in self-testing for double data rate input/output