Amlan Majumdar

Person

White Plains, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for fabricating transistor with thinned channel
- Patent number 11,978,799
- Issue date May 7, 2024
- Tahoe Research, LTD.
- Justin K. Brask
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device isolation using preferential oxidation of the bulk substrate
- Patent number 10,978,562
- Issue date Apr 13, 2021
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating transistor with thinned channel
- Patent number 10,937,907
- Issue date Mar 2, 2021
- Intel Corporation
- Justin K. Brask
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V transistor device with self-aligned doped bottom barrier
- Patent number 10,937,871
- Issue date Mar 2, 2021
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device isolation using preferential oxidation of the bulk substrate
- Patent number 10,559,666
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating transistor with thinned channel
- Patent number 10,367,093
- Issue date Jul 30, 2019
- Justin K. Brask
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hybrid III-V technology to support multiple supply voltages and off...
- Patent number 10,366,892
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device isolation using preferential oxidation of the bulk substrate
- Patent number 10,249,719
- Issue date Apr 2, 2019
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device isolation using preferential oxidation of the bulk substrate
- Patent number 10,243,050
- Issue date Mar 26, 2019
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Extreme high mobility CMOS logic
- Patent number 10,141,437
- Issue date Nov 27, 2018
- Intel Corporation
- Suman Datta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V field effect transistor on a dielectric layer
- Patent number 10,014,377
- Issue date Jul 3, 2018
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication process for mitigating external resistance of a multiga...
- Patent number 9,985,113
- Issue date May 29, 2018
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V transistor device with self-aligned doped bottom barrier
- Patent number 9,941,363
- Issue date Apr 10, 2018
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid III-V technology to support multiple supply voltages and off...
- Patent number 9,922,830
- Issue date Mar 20, 2018
- International Business Machines Corporation
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planar III-V field effect transistor (FET) on dielectric layer
- Patent number 9,882,021
- Issue date Jan 30, 2018
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device isolation using preferential oxidation of the bulk substrate
- Patent number 9,865,688
- Issue date Jan 9, 2018
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating transistor with thinned channel
- Patent number 9,806,195
- Issue date Oct 31, 2017
- Intel Corporation
- Justin K. Brask
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Asymmetric III-V MOSFET on silicon substrate
- Patent number 9,773,903
- Issue date Sep 26, 2017
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device structures and methods of forming semiconducto...
- Patent number 9,761,724
- Issue date Sep 12, 2017
- Intel Corporation
- Justin K. Brask
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V MOSFET with strained channel and semi-insulating bottom barrier
- Patent number 9,748,357
- Issue date Aug 29, 2017
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for CMP-free III-V isolation
- Patent number 9,711,648
- Issue date Jul 18, 2017
- GLOBALFOUNDRIES Inc.
- Effendi Leobandung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V field effect transistor on a dielectric layer
- Patent number 9,704,958
- Issue date Jul 11, 2017
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Extreme high mobility CMOS logic
- Patent number 9,691,856
- Issue date Jun 27, 2017
- Intel Corporation
- Suman Datta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V semiconductor device having self-aligned contacts
- Patent number 9,666,684
- Issue date May 30, 2017
- GLOBALFOUNDRIES Inc.
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication process for mitigating external resistance of a multiga...
- Patent number 9,653,606
- Issue date May 16, 2017
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing direct source-to-drain tunneling in field effect transisto...
- Patent number 9,564,514
- Issue date Feb 7, 2017
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric III-V MOSFET on silicon substrate
- Patent number 9,553,166
- Issue date Jan 24, 2017
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V MOSFETs with halo-doped bottom barrier layer
- Patent number 9,530,860
- Issue date Dec 27, 2016
- GLOBALFOUNDRIES, INC.
- Pranita Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V field effect transistor (FET) with reduced short channel leak...
- Patent number 9,515,165
- Issue date Dec 6, 2016
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple via structure and method
- Patent number 9,508,640
- Issue date Nov 29, 2016
- GLOBALFOUNDRIES, INC.
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL
- Publication number 20210135007
- Publication date May 6, 2021
- Intel Corporation
- Justin K. Brask
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE
- Publication number 20200144375
- Publication date May 7, 2020
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL
- Publication number 20190371940
- Publication date Dec 5, 2019
- Intel Corporation
- Justin K. Brask
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE
- Publication number 20190165109
- Publication date May 30, 2019
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hybrid III-V Technology to Support Multiple Supply Voltages and Off...
- Publication number 20180174844
- Publication date Jun 21, 2018
- International Business Machines Corporation
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V TRANSISTOR DEVICE WITH SELF-ALIGNED DOPED BOTTOM BARRIER
- Publication number 20180151674
- Publication date May 31, 2018
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE
- Publication number 20180130884
- Publication date May 10, 2018
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE
- Publication number 20180130885
- Publication date May 10, 2018
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL
- Publication number 20180047846
- Publication date Feb 15, 2018
- Intel Corporation
- Justin K. Brask
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EXTREME HIGH MOBILITY CMOS LOGIC
- Publication number 20170309734
- Publication date Oct 26, 2017
- Intel Corporation
- Suman DATTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V FIELD EFFECT TRANSISTOR ON A DIELECTRIC LAYER
- Publication number 20170179238
- Publication date Jun 22, 2017
- International Business Machines Corporation
- CHENG-WEI CHENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V TRANSISTOR DEVICE WITH DOPED BOTTOM BARRIER
- Publication number 20170179232
- Publication date Jun 22, 2017
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V TRANSISTOR DEVICE WITH SELF-ALIGNED DOPED BOTTOM BARRIER
- Publication number 20170179288
- Publication date Jun 22, 2017
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V FIELD EFFECT TRANSISTOR ON A DIELECTRIC LAYER
- Publication number 20170179237
- Publication date Jun 22, 2017
- International Business Machines Corporation
- CHENG-WEI CHENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION PROCESS FOR MITIGATING EXTERNAL RESISTANCE OF A MULTIGA...
- Publication number 20170148896
- Publication date May 25, 2017
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYMMETRIC III-V MOSFET ON SILICON SUBSTRATE
- Publication number 20170092763
- Publication date Mar 30, 2017
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V MOSFET WITH STRAINED CHANNEL AND SEMI-INSULATING BOTTOM BARRIER
- Publication number 20160343826
- Publication date Nov 24, 2016
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT T...
- Publication number 20160308014
- Publication date Oct 20, 2016
- Marko Radosavljevic
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTO...
- Publication number 20160293765
- Publication date Oct 6, 2016
- Justin K. Brask
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V MOSFET WITH STRAINED CHANNEL AND SEMI-INSULATING BOTTOM BARRIER
- Publication number 20160204253
- Publication date Jul 14, 2016
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V NANOWIRE FET WITH COMPOSITIONALLY-GRADED CHANNEL AND WIDE-BAN...
- Publication number 20160197154
- Publication date Jul 7, 2016
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL
- Publication number 20160197185
- Publication date Jul 7, 2016
- Intel Corporation
- Justin K. Brask
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STATIC MEMORY CELL WITH TFET STORAGE ELEMENTS
- Publication number 20160196867
- Publication date Jul 7, 2016
- International Business Machines Corporation
- Leland Chang
- G11 - INFORMATION STORAGE
Information Patent Application
Multiple VT in III-V FETS
- Publication number 20160181277
- Publication date Jun 23, 2016
- International Business Machines Corporation
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V MOSFETS With Halo-Doped Bottom Barrier Layer
- Publication number 20160181394
- Publication date Jun 23, 2016
- International Business Machines Corporation
- Pranita Kerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOWIRE FIELD EFFECT TRANSISTOR WITH INNER AND OUTER GATES
- Publication number 20160172441
- Publication date Jun 16, 2016
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLANAR III-V FIELD EFFECT TRANSISTOR (FET) ON DIELECTRIC LAYER
- Publication number 20160172465
- Publication date Jun 16, 2016
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTO...
- Publication number 20160149050
- Publication date May 26, 2016
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL FIELD EFFECT TRANSISTORS WITH CONTROLLED OVERLAP BETWEEN G...
- Publication number 20160149054
- Publication date May 26, 2016
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTO...
- Publication number 20160149020
- Publication date May 26, 2016
- International Business Machines Corporation
- Anirban Basu
- H01 - BASIC ELECTRIC ELEMENTS

Amlan Majumdar

Person

Patents Grantslast 30 patents

Method for fabricating transistor with thinned channel

Device isolation using preferential oxidation of the bulk substrate

Method for fabricating transistor with thinned channel

III-V transistor device with self-aligned doped bottom barrier

Device isolation using preferential oxidation of the bulk substrate

Method for fabricating transistor with thinned channel

Hybrid III-V technology to support multiple supply voltages and off...

Device isolation using preferential oxidation of the bulk substrate

Device isolation using preferential oxidation of the bulk substrate

Extreme high mobility CMOS logic

III-V field effect transistor on a dielectric layer

Fabrication process for mitigating external resistance of a multiga...

III-V transistor device with self-aligned doped bottom barrier

Hybrid III-V technology to support multiple supply voltages and off...

Planar III-V field effect transistor (FET) on dielectric layer

Device isolation using preferential oxidation of the bulk substrate

Method for fabricating transistor with thinned channel

Asymmetric III-V MOSFET on silicon substrate

Semiconductor device structures and methods of forming semiconducto...

III-V MOSFET with strained channel and semi-insulating bottom barrier

Structure and method for CMP-free III-V isolation

III-V field effect transistor on a dielectric layer

Extreme high mobility CMOS logic

III-V semiconductor device having self-aligned contacts

Fabrication process for mitigating external resistance of a multiga...

Reducing direct source-to-drain tunneling in field effect transisto...

Asymmetric III-V MOSFET on silicon substrate

III-V MOSFETs with halo-doped bottom barrier layer

III-V field effect transistor (FET) with reduced short channel leak...

Multiple via structure and method

Patents Applicationslast 30 patents

METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL

DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE

METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL

DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE

Hybrid III-V Technology to Support Multiple Supply Voltages and Off...

III-V TRANSISTOR DEVICE WITH SELF-ALIGNED DOPED BOTTOM BARRIER

DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE

DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE

METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL

EXTREME HIGH MOBILITY CMOS LOGIC

III-V FIELD EFFECT TRANSISTOR ON A DIELECTRIC LAYER

III-V TRANSISTOR DEVICE WITH DOPED BOTTOM BARRIER

III-V TRANSISTOR DEVICE WITH SELF-ALIGNED DOPED BOTTOM BARRIER

III-V FIELD EFFECT TRANSISTOR ON A DIELECTRIC LAYER

FABRICATION PROCESS FOR MITIGATING EXTERNAL RESISTANCE OF A MULTIGA...

ASYMMETRIC III-V MOSFET ON SILICON SUBSTRATE

III-V MOSFET WITH STRAINED CHANNEL AND SEMI-INSULATING BOTTOM BARRIER

FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT T...

SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTO...

III-V MOSFET WITH STRAINED CHANNEL AND SEMI-INSULATING BOTTOM BARRIER

III-V NANOWIRE FET WITH COMPOSITIONALLY-GRADED CHANNEL AND WIDE-BAN...

METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL

STATIC MEMORY CELL WITH TFET STORAGE ELEMENTS

Multiple VT in III-V FETS

III-V MOSFETS With Halo-Doped Bottom Barrier Layer

NANOWIRE FIELD EFFECT TRANSISTOR WITH INNER AND OUTER GATES

PLANAR III-V FIELD EFFECT TRANSISTOR (FET) ON DIELECTRIC LAYER

REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTO...

VERTICAL FIELD EFFECT TRANSISTORS WITH CONTROLLED OVERLAP BETWEEN G...

REDUCING DIRECT SOURCE-TO-DRAIN TUNNELING IN FIELD EFFECT TRANSISTO...