Patent Application
20170179232
The present invention generally relates to metal oxide semiconductor field effect transistor (MOSFET) devices, and more specifically, to MOSFET devices with a doped bottom barrier layer.
The MOSFET is a transistor used for amplifying or switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or glass, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
N-type field effect transistors (NFET) and p-type field effect transistors (PFET) are two types of complementary MOSFETs. The NFET uses electrons as the current carriers and with n-doped source and drain junctions. The PFET uses holes as the current carriers and with p-doped source and drain junctions.
In conventional III-V MOSFET devices, short-channel effects are improved by incorporating a heavily doped p-type bottom barrier layer. The heavily doped p-type bottom barrier layer is often epitaxially grown entirely under the source/drain contact region.
According to an embodiment of the present invention, a method for forming a semiconductor device comprising forming a sacrificial gate stack on a channel region of first layer of a substrate, forming a spacer adjacent to the sacrificial gate stack, forming a raised source/drain region on the first layer of the substrate adjacent to the spacer, forming a dielectric layer over the raised source/drain region, removing the sacrificial gate stack to expose the channel region of the first layer of the substrate, and implanting dopants in a second layer of the substrate to form an implant region in the second layer below the channel region of the first layer of the substrate, where the first layer of the substrate is arranged on the second layer of the substrate.
According to another embodiment of the present invention, a method for forming a semiconductor device comprises forming a sacrificial gate stack on a channel region of first layer of a substrate, forming a spacer adjacent to the sacrificial gate stack, removing exposed portions of the first layer of the substrate to expose portions of a second layer of the substrate, forming an insulator region on portions of the second layer of the substrate, forming a raised source/drain region on the second layer of the substrate adjacent to the spacer, forming a dielectric layer over the raised source/drain region, removing the sacrificial gate stack to expose the channel region of the first layer of the substrate, and implanting dopants in a second layer of the substrate to form an implant region in the second layer below the channel region of the first layer of the substrate, where the first layer of the substrate is arranged on the second layer of the substrate.
According to yet another embodiment of the present invention, a semiconductor device comprises a gate stack arranged on a channel region of a first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an epitaxially grown source/drain region arranged on the first layer of the substrate adjacent to the spacer, and an implant region arranged below the channel region of the first layer of the substrate, the implant region arranged in a second layer of the substrate, the first layer of the substrate arranged on the second layer of the substrate.
As discussed above, conventional III-V MOSFET devices, short-channel effects are improved by incorporating a heavily doped p-type bottom barrier layer. The heavily doped p-type bottom barrier layer is often epitaxially grown entirely under the source/drain contact region.
The embodiments described herein provide for III-V MOSFET structures with a p-type doped bottom barrier layer that is self-aligned to the channel region below the gate. The embodiments described herein have desirably low junction capacitance and low band-to-band tunneling currents in the off state in low-bandgap III-V materials.
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
As used herein, the articles “a” and “an” preceding an element or component are intended to be nonrestrictive regarding the number of instances (i.e. occurrences) of the element or component. Therefore, “a” or “an” should be read to include one or at least one, and the singular word form of the element or component also includes the plural unless the number is obviously meant to be singular.
As used herein, the terms “invention” or “present invention” are non-limiting terms and not intended to refer to any single aspect of the particular invention but encompass all possible aspects as described in the specification and the claims.
As used herein, the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrates or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in the manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. In one aspect, the term “about” means within 10% of the reported numerical value. In another aspect, the term “about” means within 5% of the reported numerical value. Yet, in another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.
It will also be understood that when an element, such as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present, and the element is in contact with another element.
It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
In this regard,
The bottom barrier layer 104 is a semiconductor material with electron affinity that is less than the electron affinity of the channel layer 106 such that the conduction band of the channel layer 106 is lower in energy than the conduction band of the bottom barrier layer 104. Therefore, the higher-energy bottom barrier layer 104 acts as an energy barrier and the conduction electrons are confined to the lower-energy channel layer 106. Examples of channel/barrier material combinations are, but not limited to, InGaAs/InAlAs, InGaAs/AlGaAs, InGaAs/InP, InAs/InAlAs, InAs/AlGaAs, and InAs/InP.
Non-limiting examples of suitable oxide materials for the STI regions 302 include silicon dioxide, tetraethylorthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, silicon oxide, high temperature oxide (HTO), high density plasma (HDP) oxide, oxides formed by an atomic layer deposition (ALD) process, or any combination thereof.
The spacers 404 may be formed by, for example, depositing a layer of spacer material over exposed portions of the III-V channel layer 106 and over the sacrificial gate stack 402. The spacer material can be any dielectric spacer material. Non-limiting examples of suitable materials for the spacers 404 include dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxynitrides, or any combination thereof. The spacer material is deposited by a deposition process, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). Following the deposition of the spacer material, an etching process such as, for example reactive ion etching is performed that removes portions of the spacer material to form the spacers 404.
The high-k dielectric material layer 1002 may be formed by suitable deposition processes, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other like processes. The thickness of the high-k dielectric material may vary depending on the deposition process as well as the composition and number of high-k dielectric materials used. The high-k dielectric material layer 1002 may have a thickness in a range from about 0.5 to about 20 nm.
The work function metal(s) 1004 may be disposed over the high-k dielectric material. The type of work function metal(s) depends on the type of transistor and may differ between the NFET 101 and the PFET 102. Non-limiting examples of suitable work function metals 1004 include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof.
A conductive metal (not shown) is deposited over the high-k dielectric material(s) and workfunction layer(s) to form the gate stacks. Non-limiting examples of suitable conductive metals include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive metal may be deposited by a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, and sputtering.
A planarization process, for example, chemical mechanical planarization (CMP), is performed to polish the surface of the conductive gate metal.
Following the formation of the gate stack 1001, contacts 1006 are formed by forming contact trenches (not shown) in the ILD layer 802 that expose portions of the silicide 702 using a suitable patterning and etching process such as, for example, reactive ion etching. Following the formation of the contact trenches, a liner layer (not shown) may be deposited in the contact trenches. Conductive material is deposited in the contact trenches and planarized using a planarization process such as, for example, chemical mechanical polishing that defines the contacts 1006. The conductive material may include, for example, copper, aluminum, silver, or other suitable conductive materials.
Referring to
Following the formation of the spacers 404, source/drain extension regions 1302 may be formed in the III-V channel layer 106 using, for example, an ion implantation and annealing process as described above. A channel region 1206 in the III-V channel layer 106 is shown under the sacrificial gate stack 404.
The embodiments described herein provide for III-V MOSFET structures with a p-type doped bottom barrier layer that is self-aligned to the channel region below the gate. The embodiments described herein have desirably low junction capacitance and low band-to-band tunneling currents in the off state in low-bandgap III-V materials.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
