Amos Ben-Meir

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-stage address translation for a computing device
- Patent number 10,210,096
- Issue date Feb 19, 2019
- Ampere Computing LLC
- Amos Ben-Meir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing table lookup
- Patent number 9,058,284
- Issue date Jun 16, 2015
- Applied Micro Circuits Corporation
- Amos Ben-Meir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch instruction mechanism for processor
- Patent number 6,253,306
- Issue date Jun 26, 2001
- Advanced Micro Devices, Inc.
- Amos Ben-Meir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified multi-function operation scheduler for out-of-order executi...
- Patent number 6,195,744
- Issue date Feb 27, 2001
- Advanced Micro Devices, Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a coincident rising edge detection circuit
- Patent number 6,194,927
- Issue date Feb 27, 2001
- Advanced Micro Devices, Inc.
- Matthew P. Crowley
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integration of multi-stage execution units with a scheduler for sin...
- Patent number 6,161,173
- Issue date Dec 12, 2000
- Advanced Micro Devices, Inc.
- Ravi Krishna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with short set-up and hold times for bus signals
- Patent number 6,047,382
- Issue date Apr 4, 2000
- Advanced Micro Devices, Inc.
- Reading G. Maley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan chains for out-of-order load/store execution control
- Patent number 6,038,657
- Issue date Mar 14, 2000
- Advanced Micro Devices, Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-timed pulse control circuit
- Patent number 5,964,884
- Issue date Oct 12, 1999
- Advanced Micro Devices, Inc.
- Hamid Partovi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register-based redundancy circuit and method for built-in self-repa...
- Patent number 5,920,515
- Issue date Jul 6, 1999
- Advanced Micro Devices, Inc.
- Imtiaz P. Shaik
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross clock domain clocking for a system using two clock frequencie...
- Patent number 5,915,107
- Issue date Jun 22, 1999
- Advanced Micro Devices, Inc.
- Reading G. Maley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Even bus clock circuit
- Patent number 5,898,640
- Issue date Apr 27, 1999
- Advanced Micro Devices, Inc.
- Amos Ben-Meir
- G11 - INFORMATION STORAGE
Information Patent Grant
Unified multi-function operation scheduler for out-of-order executi...
- Patent number 5,884,059
- Issue date Mar 16, 1999
- Advanced Micro Devices, Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system that rapidly indentifies first or second operatio...
- Patent number 5,881,261
- Issue date Mar 9, 1999
- Advanced Micro Devices, Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-modifying code handling system
- Patent number 5,826,073
- Issue date Oct 20, 1998
- Advanced Micro Devices, Inc.
- Amos Ben-Meir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction predecode and multiple instruction decode
- Patent number 5,809,273
- Issue date Sep 15, 1998
- Advanced Micro Devices, Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Out-of-order processing that removes an issued operation from an ex...
- Patent number 5,799,165
- Issue date Aug 25, 1998
- Advanced Micro Devices, Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Out-of-order load/store execution control
- Patent number 5,754,812
- Issue date May 19, 1998
- Advanced Micro Devices, Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan chain for rapidly identifying first or second objects of selec...
- Patent number 5,745,724
- Issue date Apr 28, 1998
- Advanced Micro Devices, Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-STAGE ADDRESS TRANSLATION FOR A COMPUTING DEVICE
- Publication number 20150095610
- Publication date Apr 2, 2015
- Applied Micro Circuits Corporation
- Amos Ben-Meir
- G06 - COMPUTING CALCULATING COUNTING

Amos Ben-Meir

Person

Patents Grantslast 30 patents

Multi-stage address translation for a computing device

Method and apparatus for performing table lookup

Prefetch instruction mechanism for processor

Unified multi-function operation scheduler for out-of-order executi...

Apparatus and method for a coincident rising edge detection circuit

Integration of multi-stage execution units with a scheduler for sin...

Processor with short set-up and hold times for bus signals

Scan chains for out-of-order load/store execution control

Self-timed pulse control circuit

Register-based redundancy circuit and method for built-in self-repa...

Cross clock domain clocking for a system using two clock frequencie...

Even bus clock circuit

Unified multi-function operation scheduler for out-of-order executi...

Processing system that rapidly indentifies first or second operatio...

Self-modifying code handling system

Instruction predecode and multiple instruction decode

Out-of-order processing that removes an issued operation from an ex...

Out-of-order load/store execution control

Scan chain for rapidly identifying first or second objects of selec...

Patents Applicationslast 30 patents

MULTI-STAGE ADDRESS TRANSLATION FOR A COMPUTING DEVICE