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Andrew K. Percey
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Sunnyvale, CA, US
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last 30 patents
Information
Patent Grant
Synchronized multi-output digital clock manager
Patent number
7,187,742
Issue date
Mar 6, 2007
Xilinx, Inc.
John D. Logue
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Multi-speed delay-locked loop
Patent number
7,098,710
Issue date
Aug 29, 2006
Xilinx, Inc.
Bernard J. New
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Phase matched clock divider
Patent number
7,046,052
Issue date
May 16, 2006
Xilinx, Inc.
Andrew K. Percey
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Digital spread spectrum circuitry
Patent number
7,010,014
Issue date
Mar 7, 2006
Xilinx, Inc.
Andrew K. Percey
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and apparatus for clock signal performance measurement
Patent number
6,983,394
Issue date
Jan 3, 2006
Xilinx, Inc.
Shawn K. Morrison
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Digital phase shifter
Patent number
6,775,342
Issue date
Aug 10, 2004
Xilinx, Inc.
Steven P. Young
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and apparatus for controlling supply voltage levels for inte...
Patent number
6,737,925
Issue date
May 18, 2004
Xilinx, Inc.
John D. Logue
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Glitchless delay line using gray code multiplexer
Patent number
6,400,735
Issue date
Jun 4, 2002
Xilinx, Inc.
Andrew K. Percey
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Input/output interconnect circuit for FPGAs
Patent number
6,204,689
Issue date
Mar 20, 2001
Xilinx, Inc.
Andrew K. Percey
H03 - BASIC ELECTRONIC CIRCUITRY