Andrew Lines

Person

Calabasas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Energy efficient memory array with optimized burst read and write d...
- Patent number 11,908,542
- Issue date Feb 20, 2024
- Intel Corporation
- Charles Augustine
- G11 - INFORMATION STORAGE
Information Patent Grant
Trace-based neuromorphic architecture for advanced learning
- Patent number 11,037,054
- Issue date Jun 15, 2021
- Intel Corporation
- Michael I Davies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neuromorphic core and chip traffic control
- Patent number 10,810,488
- Issue date Oct 20, 2020
- Intel Corporation
- Michael I Davies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary search pipeline
- Patent number 8,954,661
- Issue date Feb 10, 2015
- Intel Corporation
- Andrew Lines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level domino, bundled data, and mixed templates
- Patent number 8,495,543
- Issue date Jul 23, 2013
- University of Southern California
- Georgios Dimou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clustering and fanout optimizations of asynchronous circuits
- Patent number 8,448,105
- Issue date May 21, 2013
- University of Southern California
- Georgios Dimou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo dual-port SRAM and a shared memory switch using multiple mem...
- Patent number 8,370,557
- Issue date Feb 5, 2013
- Intel Corporation
- Jonathan Dama
- G11 - INFORMATION STORAGE
Information Patent Grant
Power aware asynchronous circuits
- Patent number 8,086,975
- Issue date Dec 27, 2011
- University of Southern California
- Ken Shiring
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic synthesis of multi-level domino asynchronous pipelines
- Patent number 8,051,396
- Issue date Nov 1, 2011
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reshuffled communications processes in pipelined asynchronous circuits
- Patent number 7,934,031
- Issue date Apr 26, 2011
- California Institute of Technology
- Andrew M. Lines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared-memory switch fabric architecture
- Patent number 7,814,280
- Issue date Oct 12, 2010
- Fulcrum Microsystems Inc.
- Uri Cummings
- G11 - INFORMATION STORAGE
Information Patent Grant
Asynchronous multiple-order issue system architecture
- Patent number 7,698,535
- Issue date Apr 13, 2010
- Fulcrum Microsystems, Inc.
- Andrew Lines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic synthesis of multi-level domino asynchronous pipelines
- Patent number 7,584,449
- Issue date Sep 1, 2009
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous crossbar with deterministic or arbitrated control
- Patent number 7,283,557
- Issue date Oct 16, 2007
- Fulcrum Microsystems, Inc.
- Uri Cummings
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Asynchronous crossbar with deterministic or arbitrated control
- Patent number 7,274,709
- Issue date Sep 25, 2007
- Fulcrum Microsystems, Inc.
- Uri Cummings
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Asynchronous crossbar with deterministic or arbitrated control
- Patent number 7,274,710
- Issue date Sep 25, 2007
- Fulcrum Microsystems, Inc.
- Uri Cummings
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Asynchronous system-on-a-chip interconnect
- Patent number 7,239,669
- Issue date Jul 3, 2007
- Fulcrum Microsystems, Inc.
- Uri Cummings
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous static random access memory
- Patent number 7,161,828
- Issue date Jan 9, 2007
- Fulcrum Microsystems, Inc.
- Uri Cummings
- G11 - INFORMATION STORAGE
Information Patent Grant
Asynchronous static random access memory
- Patent number 7,050,324
- Issue date May 23, 2006
- Fulcrum Microsystems, Inc.
- Uri Cummings
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for facilitating conversion between asynchronous and syn...
- Patent number 6,961,863
- Issue date Nov 1, 2005
- Fulcrum Microsystems Inc.
- Michael I. Davies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for facilitating conversion between asynchronous and syn...
- Patent number 6,950,959
- Issue date Sep 27, 2005
- Fulcrum Microystems Inc.
- Michael I. Davies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for facilitating physical synthesis of an int...
- Patent number 6,785,875
- Issue date Aug 31, 2004
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined asynchronous processing
- Patent number 6,658,550
- Issue date Dec 2, 2003
- California Institute of Technology
- Alain J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous circuits with pipelined completion process
- Patent number 6,502,180
- Issue date Dec 31, 2002
- California Institute of Technology
- Alain J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined asynchronous processing
- Patent number 6,381,692
- Issue date Apr 30, 2002
- California Institute of Technology
- Alain J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined completion for asynchronous communication
- Patent number 6,038,656
- Issue date Mar 14, 2000
- California Institute of Technology
- Alain J. Martin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TRACE-BASED NEUROMORPHIC ARCHITECTURE FOR ADVANCED LEARNING
- Publication number 20210304005
- Publication date Sep 30, 2021
- Intel Corporation
- Michael I. Davies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENERGY EFFICIENT MEMORY ARRAY WITH OPTIMIZED BURST READ AND WRITE D...
- Publication number 20210193196
- Publication date Jun 24, 2021
- Intel Corporation
- Charles Augustine
- G11 - INFORMATION STORAGE
Information Patent Application
NEUROMORPHIC CORE AND CHIP TRAFFIC CONTROL
- Publication number 20180174032
- Publication date Jun 21, 2018
- Intel Corporation
- Michael I. Davies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACE-BASED NEUROMORPHIC ARCHITECTURE FOR ADVANCED LEARNING
- Publication number 20180174040
- Publication date Jun 21, 2018
- Michael I. Davies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BINARY SEARCH PIPELINE
- Publication number 20120110049
- Publication date May 3, 2012
- FULCRUM MICROSYSTEMS
- Andrew Lines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL DOMINO, BUNDLED DATA, AND MIXED TEMPLATES
- Publication number 20110029941
- Publication date Feb 3, 2011
- University of Southern California
- Georgios Dimou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED-MEMORY SWITCH FABRIC ARCHITECTURE
- Publication number 20100325370
- Publication date Dec 23, 2010
- Fulcrum Microsystems Inc.
- Uri Cummings
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PSEUDO DUAL-PORTED SRAM
- Publication number 20100161892
- Publication date Jun 24, 2010
- Fulcrum Microsystems, Inc.
- Jonathan Dama
- G11 - INFORMATION STORAGE
Information Patent Application
CLUSTERING AND FANOUT OPTIMIZATIONS OF ASYNCHRONOUS CIRCUITS
- Publication number 20090288059
- Publication date Nov 19, 2009
- University of Southern California
- Georgios Dimou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER AWARE ASYNCHRONOUS CIRCUITS
- Publication number 20090288058
- Publication date Nov 19, 2009
- University of Southern California
- Ken Shiring
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC SYNTHESIS OF MULTI-LEVEL DOMINO ASYNCHRONOUS PIPELINES
- Publication number 20090217232
- Publication date Aug 27, 2009
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Asynchronous system-on-a-chip interconnect
- Publication number 20060239392
- Publication date Oct 26, 2006
- Fulcrum Microsystems, Inc., A California corporation
- Uri Cummings
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reshuffled communications processes in pipelined asynchronous circuits
- Publication number 20060212628
- Publication date Sep 21, 2006
- California Institute of Technology
- Andrew M. Lines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Shared-memory switch fabric architecture
- Publication number 20060155938
- Publication date Jul 13, 2006
- Fulcrum Microsystems, Inc.
- Uri Cummings
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Logic synthesis of multi-level domino asynchronous pipelines
- Publication number 20060120189
- Publication date Jun 8, 2006
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Asynchronous static random access memory
- Publication number 20050276095
- Publication date Dec 15, 2005
- Fulcrum Microsystems Inc.
- Uri Cummings
- G11 - INFORMATION STORAGE
Information Patent Application
Asynchronous static random access memory
- Publication number 20050024928
- Publication date Feb 3, 2005
- Fulcrum Microsystems Inc.
- Uri Cummings
- G11 - INFORMATION STORAGE
Information Patent Application
Asynchronous system-on-a-chip interconnect
- Publication number 20040151209
- Publication date Aug 5, 2004
- Fulcrum Microsystems Inc. A California corporation
- Uri Cummings
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Asynchronous multiple-order issue system architecture
- Publication number 20040111589
- Publication date Jun 10, 2004
- Fulcrum Microsystems, Inc., a California corporation
- Andrew Lines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Message transfer system
- Publication number 20040100900
- Publication date May 27, 2004
- Fulcrum Microsystems, Inc.
- Andrew Lines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for facilitating physical synthesis of an int...
- Publication number 20040034844
- Publication date Feb 19, 2004
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reshuffled communications processes in pipelined asynchronous circuits
- Publication number 20040030858
- Publication date Feb 12, 2004
- Andrew M. Lines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for facilitating conversion between asynchronous and syn...
- Publication number 20030165158
- Publication date Sep 4, 2003
- Fulcrum Microsystems Inc.
- Michael I. Davies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for facilitating conversion between asynchronous and syn...
- Publication number 20030159078
- Publication date Aug 21, 2003
- Fulcrum Microsystems Inc.
- Michael I. Davies
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Asynchronous crossbar with deterministic or arbitrated control
- Publication number 20030146073
- Publication date Aug 7, 2003
- Fulcrum Microcystems Inc. A California Corporation
- Uri Cummings
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Asynchronous crossbar with deterministic or arbitrated control
- Publication number 20030146075
- Publication date Aug 7, 2003
- Fulcrum Microsystems Inc.
- Uri Cummings
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Asynchronous crossbar with deterministic or arbitrated control
- Publication number 20030146074
- Publication date Aug 7, 2003
- Fulcrum Microsystems Inc. A California corporation
- Uri Cummings
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pipelined completion for asynchronous communication
- Publication number 20030140214
- Publication date Jul 24, 2003
- California Institute of Technology
- Alain J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelined asynchronous processing
- Publication number 20020156995
- Publication date Oct 24, 2002
- California Institute of Technology
- Alain J. Martin
- G06 - COMPUTING CALCULATING COUNTING

Andrew Lines

Person

Patents Grantslast 30 patents

Energy efficient memory array with optimized burst read and write d...

Trace-based neuromorphic architecture for advanced learning

Neuromorphic core and chip traffic control

Binary search pipeline

Multi-level domino, bundled data, and mixed templates

Clustering and fanout optimizations of asynchronous circuits

Pseudo dual-port SRAM and a shared memory switch using multiple mem...

Power aware asynchronous circuits

Logic synthesis of multi-level domino asynchronous pipelines

Reshuffled communications processes in pipelined asynchronous circuits

Shared-memory switch fabric architecture

Asynchronous multiple-order issue system architecture

Logic synthesis of multi-level domino asynchronous pipelines

Asynchronous crossbar with deterministic or arbitrated control

Asynchronous crossbar with deterministic or arbitrated control

Asynchronous crossbar with deterministic or arbitrated control

Asynchronous system-on-a-chip interconnect

Asynchronous static random access memory

Asynchronous static random access memory

Techniques for facilitating conversion between asynchronous and syn...

Techniques for facilitating conversion between asynchronous and syn...

Methods and apparatus for facilitating physical synthesis of an int...

Pipelined asynchronous processing

Asynchronous circuits with pipelined completion process

Pipelined asynchronous processing

Pipelined completion for asynchronous communication

Patents Applicationslast 30 patents

TRACE-BASED NEUROMORPHIC ARCHITECTURE FOR ADVANCED LEARNING

ENERGY EFFICIENT MEMORY ARRAY WITH OPTIMIZED BURST READ AND WRITE D...

NEUROMORPHIC CORE AND CHIP TRAFFIC CONTROL

TRACE-BASED NEUROMORPHIC ARCHITECTURE FOR ADVANCED LEARNING

BINARY SEARCH PIPELINE

MULTI-LEVEL DOMINO, BUNDLED DATA, AND MIXED TEMPLATES

SHARED-MEMORY SWITCH FABRIC ARCHITECTURE

PSEUDO DUAL-PORTED SRAM

CLUSTERING AND FANOUT OPTIMIZATIONS OF ASYNCHRONOUS CIRCUITS

POWER AWARE ASYNCHRONOUS CIRCUITS

LOGIC SYNTHESIS OF MULTI-LEVEL DOMINO ASYNCHRONOUS PIPELINES

Asynchronous system-on-a-chip interconnect

Reshuffled communications processes in pipelined asynchronous circuits

Shared-memory switch fabric architecture

Logic synthesis of multi-level domino asynchronous pipelines

Asynchronous static random access memory

Asynchronous static random access memory

Asynchronous system-on-a-chip interconnect

Asynchronous multiple-order issue system architecture

Message transfer system

Methods and apparatus for facilitating physical synthesis of an int...

Reshuffled communications processes in pipelined asynchronous circuits

Techniques for facilitating conversion between asynchronous and syn...

Techniques for facilitating conversion between asynchronous and syn...

Asynchronous crossbar with deterministic or arbitrated control

Asynchronous crossbar with deterministic or arbitrated control

Asynchronous crossbar with deterministic or arbitrated control

Pipelined completion for asynchronous communication

Pipelined asynchronous processing