Andrew N. Westmeyer

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Strained NMOS transistor featuring deep carbon doped regions and ra...
- Patent number 8,426,858
- Issue date Apr 23, 2013
- Intel Corporation
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal gate transistors with raised source and drain regions formed...
- Patent number 8,344,452
- Issue date Jan 1, 2013
- Intel Corporation
- Nick Lindert
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Strained NMOS transistor featuring deep carbon doped regions and ra...
- Patent number 7,858,981
- Issue date Dec 28, 2010
- Intel Corporation
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS transistor junction regions formed by a CVD etching and deposi...
- Patent number 7,812,394
- Issue date Oct 12, 2010
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS transistor junction regions formed by a CVD etching and deposi...
- Patent number 7,479,432
- Issue date Jan 20, 2009
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained NMOS transistor featuring deep carbon doped regions and ra...
- Patent number 7,479,431
- Issue date Jan 20, 2009
- Intel Corporation
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabricating strained channel epitaxial source/drain transistors
- Patent number 7,427,775
- Issue date Sep 23, 2008
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming an integrated circuit
- Patent number 7,402,872
- Issue date Jul 22, 2008
- Intel Corporation
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal gate transistors with epitaxial source and drain regions
- Patent number 7,332,439
- Issue date Feb 19, 2008
- Intel Corporation
- Nick Lindert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabricating strained channel epitaxial source/drain transistors
- Patent number 7,226,842
- Issue date Jun 5, 2007
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS transistor junction regions formed by a CVD etching and deposi...
- Patent number 7,195,985
- Issue date Mar 27, 2007
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
STRAINED NMOS TRANSISTOR FEATURING DEEP CARBON DOPED REGIONS AND RA...
- Publication number 20110068403
- Publication date Mar 24, 2011
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strained NMOS transistor featuring deep carbon doped regions and ra...
- Publication number 20090152601
- Publication date Jun 18, 2009
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS TRANSISTOR JUNCTION REGIONS FORMED BY A CVD ETCHING AND DEPOSI...
- Publication number 20090039390
- Publication date Feb 12, 2009
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal gate transistors with epitaxial source and drain regions
- Publication number 20080142840
- Publication date Jun 19, 2008
- Nick Lindert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fabricating strained channel epitaxial source/drain transistors
- Publication number 20070194391
- Publication date Aug 23, 2007
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS transistor junction regions formed by a CVD etching and deposi...
- Publication number 20070105331
- Publication date May 10, 2007
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS transistor junction regions formed by a CVD etching and deposi...
- Publication number 20060148151
- Publication date Jul 6, 2006
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming an integrated circuit
- Publication number 20060131665
- Publication date Jun 22, 2006
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strained NMOS transistor featuring deep carbon doped regions and ra...
- Publication number 20060134872
- Publication date Jun 22, 2006
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal gate transistors with epitaxial source and drain regions
- Publication number 20060068590
- Publication date Mar 30, 2006
- Nick Lindert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fabricating strained channel epitaxial source/drain transistors
- Publication number 20050179066
- Publication date Aug 18, 2005
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS

Andrew N. Westmeyer

Person

Patents Grantslast 30 patents

Strained NMOS transistor featuring deep carbon doped regions and ra...

Metal gate transistors with raised source and drain regions formed...

Strained NMOS transistor featuring deep carbon doped regions and ra...

CMOS transistor junction regions formed by a CVD etching and deposi...

CMOS transistor junction regions formed by a CVD etching and deposi...

Strained NMOS transistor featuring deep carbon doped regions and ra...

Fabricating strained channel epitaxial source/drain transistors

Method for forming an integrated circuit

Metal gate transistors with epitaxial source and drain regions

Fabricating strained channel epitaxial source/drain transistors

CMOS transistor junction regions formed by a CVD etching and deposi...

Patents Applicationslast 30 patents

STRAINED NMOS TRANSISTOR FEATURING DEEP CARBON DOPED REGIONS AND RA...

Strained NMOS transistor featuring deep carbon doped regions and ra...

CMOS TRANSISTOR JUNCTION REGIONS FORMED BY A CVD ETCHING AND DEPOSI...

Metal gate transistors with epitaxial source and drain regions

Fabricating strained channel epitaxial source/drain transistors

CMOS transistor junction regions formed by a CVD etching and deposi...

CMOS transistor junction regions formed by a CVD etching and deposi...

Method for forming an integrated circuit

Strained NMOS transistor featuring deep carbon doped regions and ra...

Metal gate transistors with epitaxial source and drain regions

Fabricating strained channel epitaxial source/drain transistors