Andy Chih-Hung Wei

Person

Queensbury, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit structures with gate cuts above buried power rails
- Patent number 12,327,791
- Issue date Jun 10, 2025
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate spacing in integrated circuit structures
- Patent number 12,328,936
- Issue date Jun 10, 2025
- Intel Corporation
- Guillaume Bouche
Information Patent Grant
Self-aligned lateral contacts
- Patent number 12,315,805
- Issue date May 27, 2025
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor arrangements with stacked trench contacts and gate straps
- Patent number 12,237,388
- Issue date Feb 25, 2025
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked vias with bottom portions formed using selective growth
- Patent number 12,211,786
- Issue date Jan 28, 2025
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device contact sizing in integrated circuit structures
- Patent number 12,211,898
- Issue date Jan 28, 2025
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact over active gate structures with tapered gate or trench con...
- Patent number 12,199,161
- Issue date Jan 14, 2025
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of a placeholder for backside contact formation for transistor...
- Patent number 12,148,751
- Issue date Nov 19, 2024
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried power rails with self-aligned vias to trench contacts
- Patent number 12,094,822
- Issue date Sep 17, 2024
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device contacts in integrated circuit structures
- Patent number 11,973,121
- Issue date Apr 30, 2024
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Back end of line integration for self-aligned vias
- Patent number 11,916,010
- Issue date Feb 27, 2024
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source/drain regions in integrated circuit structures
- Patent number 11,916,106
- Issue date Feb 27, 2024
- Intel Corporation
- Sean T. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation regions in integrated circuit structures
- Patent number 11,749,715
- Issue date Sep 5, 2023
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor arrangements with metal gate cuts and recessed power rails
- Patent number 11,508,847
- Issue date Nov 22, 2022
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate spacing in integrated circuit structures
- Patent number 11,482,524
- Issue date Oct 25, 2022
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Source/drain regions in integrated circuit structures
- Patent number 11,450,736
- Issue date Sep 20, 2022
- Intel Corporation
- Sean T. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device contact sizing in integrated circuit structures
- Patent number 11,430,866
- Issue date Aug 30, 2022
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation regions in integrated circuit structures
- Patent number 11,342,409
- Issue date May 24, 2022
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple fin finFET with low-resistance gate structure
- Patent number 11,264,463
- Issue date Mar 1, 2022
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple fin finFET with low-resistance gate structure
- Patent number 10,700,170
- Issue date Jun 30, 2020
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Merged gate and source/drain contacts in a semiconductor device
- Patent number 10,644,136
- Issue date May 5, 2020
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods, apparatus and system for a passthrough-based architecture
- Patent number 10,559,503
- Issue date Feb 11, 2020
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Precut metal lines
- Patent number 10,396,026
- Issue date Aug 27, 2019
- GLOBALFOUNDRIES Inc.
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus and system for a high density middle of line flow
- Patent number 10,236,350
- Issue date Mar 19, 2019
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor contacts self-aligned in two dimensions
- Patent number 10,056,373
- Issue date Aug 21, 2018
- GLOBALFOUNDRIES Inc.
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Merged gate and source/drain contacts in a semiconductor device
- Patent number 9,960,256
- Issue date May 1, 2018
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cap layer for spacer-constrained epitaxially grown material on fins...
- Patent number 9,899,268
- Issue date Feb 20, 2018
- GLOBALFOUNDRIES Inc.
- Andy C. Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cut first alternative for 2D self-aligned via
- Patent number 9,852,984
- Issue date Dec 26, 2017
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned via and air gap
- Patent number 9,842,801
- Issue date Dec 12, 2017
- GLOBALFOUNDRIES Inc.
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a high-k contact liner to improve effective via...
- Patent number 9,825,031
- Issue date Nov 21, 2017
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
STACKED VIAS WITH BOTTOM PORTIONS FORMED USING SELECTIVE GROWTH
- Publication number 20250125255
- Publication date Apr 17, 2025
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USE OF A PLACEHOLDER FOR BACKSIDE CONTACT FORMATION FOR TRANSISTOR...
- Publication number 20250022878
- Publication date Jan 16, 2025
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMAL GROUNDING IN BACKSIDE POWER SCHEMES USING CARRIER WAFERS
- Publication number 20240332126
- Publication date Oct 3, 2024
- Intel Corporation
- Andy Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING STACKED ELECTROSTATIC DISCHARG...
- Publication number 20240222360
- Publication date Jul 4, 2024
- Intel Corporation
- Andy Chih-Hung WEI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE/DRAIN REGIONS IN INTEGRATED CIRCUIT STRUCTURES
- Publication number 20240162289
- Publication date May 16, 2024
- Intel Corporation
- Sean T. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SOURCE OR DRAIN CONTACT FLYOVER
- Publication number 20240113177
- Publication date Apr 4, 2024
- Intel Corporation
- Sukru Yemenicioglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH BURIED POWER RAIL
- Publication number 20230207465
- Publication date Jun 29, 2023
- Intel Corporation
- Andy Chih-Hung WEI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS WITH SELF-ALIGNED TUB ARCHITECTURE
- Publication number 20230207704
- Publication date Jun 29, 2023
- Dan S. LAVRIC
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CONTA...
- Publication number 20230197714
- Publication date Jun 22, 2023
- Intel Corporation
- Guillaume BOUCHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING METAL GATE PLUG LANDED ON DIEL...
- Publication number 20230197819
- Publication date Jun 22, 2023
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING RAISED WALL ST...
- Publication number 20230197713
- Publication date Jun 22, 2023
- Intel Corporation
- Guillaume BOUCHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NEIGHBORING FI...
- Publication number 20230197717
- Publication date Jun 22, 2023
- Guillaume BOUCHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING MAXIMIZED CHANNEL SIZING
- Publication number 20230187494
- Publication date Jun 15, 2023
- Intel Corporation
- Sukru YEMENICIOGLU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE SPACING IN INTEGRATED CIRCUIT STRUCTURES
- Publication number 20230073304
- Publication date Mar 9, 2023
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL METAL GATE STRUCTURES ON NANORIBBON SEMICONDUCTOR DEVICES
- Publication number 20230062210
- Publication date Mar 2, 2023
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR PROTECTING INTEGRATED CIRCUITRY FROM PLASMA-INDUCED...
- Publication number 20230069107
- Publication date Mar 2, 2023
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE TIE STRUCTURES TO BURIED OR BACKSIDE POWER RAILS
- Publication number 20230067354
- Publication date Mar 2, 2023
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE CUT STRUCTURES
- Publication number 20230057326
- Publication date Feb 23, 2023
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYERED MULTI-FUNCTION SPACER STACK
- Publication number 20230052975
- Publication date Feb 16, 2023
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED LATERAL CONTACTS
- Publication number 20230032866
- Publication date Feb 2, 2023
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROTECTIVE LAYER FOR GATE CAP REINFORCEMENT
- Publication number 20220415736
- Publication date Dec 29, 2022
- Intel Corporation
- Guillaume BOUCHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN TO FIN TRENCH CONTACT THROUGH A METAL GATE CUT
- Publication number 20220416057
- Publication date Dec 29, 2022
- Intel Corporation
- Guillaume BOUCHE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INVERSE TAPER VIA TO SELF-ALIGNED GATE CONTACT
- Publication number 20220415792
- Publication date Dec 29, 2022
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER RAIL BETWEEN FINS OF A TRANSISTOR STRUCTURE
- Publication number 20220415796
- Publication date Dec 29, 2022
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BURIED POWER RAIL WITH A SILICIDE LAYER FOR WELL BIASING
- Publication number 20220416017
- Publication date Dec 29, 2022
- Intel Corporation
- Changyok PARK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE CONTACT SIZING IN INTEGRATED CIRCUIT STRUCTURES
- Publication number 20220359658
- Publication date Nov 10, 2022
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE/DRAIN REGIONS IN INTEGRATED CIRCUIT STRUCTURES
- Publication number 20220344459
- Publication date Oct 27, 2022
- Intel Corporation
- Sean T. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH GATE CUTS ABOVE BURIED POWER RAILS
- Publication number 20220310514
- Publication date Sep 29, 2022
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED VIAS WITH BOTTOM PORTIONS FORMED USING SUBTRACTIVE PATTERNING
- Publication number 20220293516
- Publication date Sep 15, 2022
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED VIAS WITH BOTTOM PORTIONS FORMED USING SELECTIVE GROWTH
- Publication number 20220293517
- Publication date Sep 15, 2022
- Intel Corporation
- Andy Chih-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS

Andy Chih-Hung Wei

Person

Patents Grantslast 30 patents

Integrated circuit structures with gate cuts above buried power rails

Gate spacing in integrated circuit structures

Self-aligned lateral contacts

Transistor arrangements with stacked trench contacts and gate straps

Stacked vias with bottom portions formed using selective growth

Device contact sizing in integrated circuit structures

Contact over active gate structures with tapered gate or trench con...

Use of a placeholder for backside contact formation for transistor...

Buried power rails with self-aligned vias to trench contacts

Device contacts in integrated circuit structures

Back end of line integration for self-aligned vias

Source/drain regions in integrated circuit structures

Isolation regions in integrated circuit structures

Transistor arrangements with metal gate cuts and recessed power rails

Gate spacing in integrated circuit structures

Source/drain regions in integrated circuit structures

Device contact sizing in integrated circuit structures

Isolation regions in integrated circuit structures

Multiple fin finFET with low-resistance gate structure

Multiple fin finFET with low-resistance gate structure

Merged gate and source/drain contacts in a semiconductor device

Methods, apparatus and system for a passthrough-based architecture

Precut metal lines

Method, apparatus and system for a high density middle of line flow

Transistor contacts self-aligned in two dimensions

Merged gate and source/drain contacts in a semiconductor device

Cap layer for spacer-constrained epitaxially grown material on fins...

Cut first alternative for 2D self-aligned via

Self-aligned via and air gap

Methods of forming a high-k contact liner to improve effective via...

Patents Applicationslast 30 patents

STACKED VIAS WITH BOTTOM PORTIONS FORMED USING SELECTIVE GROWTH

USE OF A PLACEHOLDER FOR BACKSIDE CONTACT FORMATION FOR TRANSISTOR...

THERMAL GROUNDING IN BACKSIDE POWER SCHEMES USING CARRIER WAFERS

INTEGRATED CIRCUIT STRUCTURES HAVING STACKED ELECTROSTATIC DISCHARG...

SOURCE/DRAIN REGIONS IN INTEGRATED CIRCUIT STRUCTURES

STACKED SOURCE OR DRAIN CONTACT FLYOVER

INTEGRATED CIRCUIT STRUCTURE WITH BURIED POWER RAIL

INTEGRATED CIRCUITS WITH SELF-ALIGNED TUB ARCHITECTURE

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING BACKSIDE CONTA...

INTEGRATED CIRCUIT STRUCTURES HAVING METAL GATE PLUG LANDED ON DIEL...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING RAISED WALL ST...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NEIGHBORING FI...

INTEGRATED CIRCUIT STRUCTURES HAVING MAXIMIZED CHANNEL SIZING

GATE SPACING IN INTEGRATED CIRCUIT STRUCTURES

DUAL METAL GATE STRUCTURES ON NANORIBBON SEMICONDUCTOR DEVICES

TECHNIQUES FOR PROTECTING INTEGRATED CIRCUITRY FROM PLASMA-INDUCED...

GATE TIE STRUCTURES TO BURIED OR BACKSIDE POWER RAILS

SELF-ALIGNED GATE CUT STRUCTURES

MULTI-LAYERED MULTI-FUNCTION SPACER STACK

SELF-ALIGNED LATERAL CONTACTS

PROTECTIVE LAYER FOR GATE CAP REINFORCEMENT

FIN TO FIN TRENCH CONTACT THROUGH A METAL GATE CUT

INVERSE TAPER VIA TO SELF-ALIGNED GATE CONTACT

POWER RAIL BETWEEN FINS OF A TRANSISTOR STRUCTURE

BURIED POWER RAIL WITH A SILICIDE LAYER FOR WELL BIASING

DEVICE CONTACT SIZING IN INTEGRATED CIRCUIT STRUCTURES

SOURCE/DRAIN REGIONS IN INTEGRATED CIRCUIT STRUCTURES

INTEGRATED CIRCUIT STRUCTURES WITH GATE CUTS ABOVE BURIED POWER RAILS

STACKED VIAS WITH BOTTOM PORTIONS FORMED USING SUBTRACTIVE PATTERNING

STACKED VIAS WITH BOTTOM PORTIONS FORMED USING SELECTIVE GROWTH