This disclosure relates generally to the field of semiconductor devices, and more specifically, to metallization stacks with integrated vias.
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each device and each interconnect becomes increasingly significant.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.
Overview
The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
For purposes of illustrating IC structures with one or more stacked vias with bottom portions formed using subtractive patterning for improved via integration in the back-end-of-line (BEOL) as described herein, it might be useful to first understand phenomena that may come into play in such arrangements. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.
ICs commonly include electrically conductive microelectronic structures, known in the art as interconnects, to provide electrical connectivity between various components. In this context, the term “metallization stack” may be used to describe a stacked series of layers of electrically conductive wires (sometimes referred to as “metal lines”) which are electrically insulated from one another except for when/where they may need to be electrically connected. In a typical metallization stack, electrical connections between metal lines of different layers of a metallization stack (such layers sometimes referred to as “metal layers” or “metallization layers”) are realized by means of vias filled with one or more electrically conductive materials, extending in a direction substantially perpendicular to the planes of the metal lines (i.e., extending in a vertical direction if the plane of the metal lines is considered to be a horizontal plane). Such vias are, therefore, integrated within the metallization stacks.
In the past, the sizes and the spacing of interconnects such as metal lines and vias have progressively decreased, and it is expected that in the future the sizes and the spacing of the interconnects will continue to progressively decrease, for at least some types of ICs (e.g., advanced microprocessors, chipset components, graphics chips, etc.). One measure of a size of a metal line is the critical dimension of the line width. One measure of the spacing of the metal lines is the line pitch, representing the center-to-center distance between the closest adjacent metal lines of a given layer of a metallization stack.
Smaller and smaller sizes and spacing of interconnects demands that performance of every interconnect is optimized. Particularly challenging are so-called “transition vias”, which are vias that provide electrical connectivity between metal layers of different pitches. Typically, lower metal layers (i.e., layers of metallization stacks which are closer to the front-end-of line (FEOL) devices, such as transistors) are denser (i.e., have smaller pitches) than upper metal layers, which may be attributed to the lower metal layers having to provide electrical connectivity to various portions of a vast number of FEOL devices. For example, lower metal layers may have pitches on the order of 18-22 nanometers, while upper metal layers may have pitches on the order of 35-40 nanometers. Transition vias need to be designed to allow for the pitch transition, as well as the change in patterning strategy used to form metal lines of lower and upper metal layers (e.g., lower, denser metal lines may command innovative and more expensive fabrication processes while metal liners of upper layers may use classic Damascene fabrication).
Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers provided over a support structure (e.g., a substrate, a wafer, or a chip), where the first metallization layer includes a bottom metal line, the second metallization layer includes a top metal line, and the first metallization layer is between the support structure and the second metallization layer. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using subtractive patterning, while the top via portion may be formed using a different fabrication technique, such as Damascene (e.g., dual Damascene) fabrication. Such a stacked via with a bottom portion formed using subtractive patterning may be particularly beneficial when used as a transition via. However, in general, stacked vias described herein are not limited to providing electrical connectivity between metal lines of metallization layers of different pitches (i.e., in various embodiments, the pitch of the first metallization layer that includes the bottom metal line as described herein may be the same or different from the pitch of the second metallization layer that includes the top metal line as described herein). Therefore, descriptions provided herein with reference to “transition vias” are equally applicable to stacked vias providing electrical connectivity between metal lines of different metallization layers of the same pitches.
As used herein, the term “bottom metal line” refers to any electrically conductive structure/line that is provided in a layer of a metallization stack that is closer to the support structure than another layer of the metallization stack, while the term “top metal line” refers to any electrically conductive structure/line that is provided in the layer of the metallization stack that is above the layer of the bottom metal lines. In other words, the bottom metal lines are provided in a layer of the metallization stack that is between the support structure and the layer in which the top metal lines are provided. In various embodiments, such bottom and top metal lines may include electrically conductive structures other than lines/trenches (e.g., at least a portion of the bottom metal line may be a gate contact), and/or may be formed, or include, electrically conductive materials other than metals.
IC structures as described herein, in particular IC structures (e.g., metallization stacks) with one or more stacked vias with bottom portions formed using subtractive patterning as described herein, may be used for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.
For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Further, references are made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,
In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, this is simply for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. Therefore, it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Furthermore, although a certain number of a given element may be illustrated in some of the drawings (e.g., a certain number of bottom metal lines, a certain number of top metal lines, a certain number of stacked vias, etc.), this is simply for ease of illustration, and more, or less, than that number may be included in an IC structure with one or more stacked vias with bottom portions formed using subtractive patterning as described herein. Still further, various views shown in some of the drawings are intended to show relative arrangements of various elements therein. In other embodiments, various IC structures with one or more stacked vias with bottom portions formed using subtractive patterning as described herein, or portions thereof, may include other elements or components that are not illustrated (e.g., transistor portions, various components that may be in electrical contact with any of the metal lines, etc.). Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using e.g., Physical Failure Analysis (PFA) would allow determination of presence of IC structures with one or more stacked vias with bottom portions formed using subtractive patterning as described herein.
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. These operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. The terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side” to explain various features of the drawings, but these terms are simply for ease of discussion, and do not imply a desired or required orientation. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art.
For example, a term “interconnect” may be used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In general, the “interconnect” may refer to both conductive lines/wires (also sometimes referred to as “lines” or “metal lines” or “trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). In general, a term “conductive line” may be used to describe an electrically conductive element isolated by a dielectric material typically comprising an interlayer low-k dielectric that is provided within the plane of an IC chip. Such conductive lines are typically arranged in several levels, or several layers, of metallization stacks. On the other hand, the term “conductive via” may be used to describe an electrically conductive element that interconnects two or more conductive lines of different levels of a metallization stack. To that end, a via may be provided substantially perpendicularly to the plane of an IC chip or a support structure over which an IC structure is provided and may interconnect two conductive lines in adjacent levels or two conductive lines in not adjacent levels. A term “metallization stack” may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC chip.
In another example, if used, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die,” the term “insulating” means “electrically insulating,” the term “conducting” means “electrically conducting,” unless otherwise specified. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “an electrically conductive material” may include one or more electrically conductive materials.
In another example, if used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide.
Furthermore, the term “connected” may be used to describe a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” may be used to describe either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” may be used to describe one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.
Example Fabrication Method
Although the operations of the method 100 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture, substantially simultaneously, multiple stacked vias with bottom portions formed using subtractive patterning within a single IC structure or multiple IC structures with stacked vias with bottom portions formed using subtractive patterning as described herein. In another example, the operations may be performed in a different order to reflect the structure of a particular device assembly in which one or more stacked vias with bottom portions formed using subtractive patterning as described herein will be included.
In addition, the example manufacturing method 100 may include other operations not specifically shown in
Various operations of the method 100 may be illustrated with reference to the example embodiments shown in
A number of elements referred to in the description of
Turning to
In general, implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V, group II-VI, or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which an IC may be built falls within the spirit and scope of the present disclosure. In various embodiments, the support structure 202 may include any such substrate, possibly with some layers (e.g., lower level metallization layers) and/or devices already formed thereon (e.g., FEOL devices), not specifically shown in the present figures, providing a suitable surface for forming metallization stacks that may include one or more stacked vias with bottom portions formed using subtractive patterning for improved via integration in the BEOL.
In general, various electrically conductive materials described herein, e.g., the M1 material 204, may include one or more of any suitable electrically conductive materials (conductors). Such materials may include any suitable electrically conductive material, alloy, or a stack of multiple electrically conductive materials. In some embodiments, various electrically conductive materials described herein may include one or more metals or metal alloys, with metals such as copper, ruthenium, palladium, platinum, cobalt, nickel, molybdenum, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, various electrically conductive materials described herein may include one or more electrically conductive alloys, oxides (e.g., conductive metal oxides), carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide, tungsten, tungsten carbide), or nitrides (e.g., hafnium nitride, zirconium nitride, titanium nitride, tantalum nitride, and aluminum nitride) of one or more metals. Various electrically conductive materials described herein, e.g., the M1 material 204, may be deposited using a deposition technique such as, but not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) (e.g., evaporative deposition, magnetron sputtering, or e-beam deposition), plasma enhanced CVD (PECVD), or electroplating.
In general, various mask materials described herein, e.g., the HM1 material 206, may include one or more of any suitable materials that may be sufficiently etch-selective with respect to one or more surrounding materials in order to serve as a mask for patterning the one or more surrounding materials. As is known in the field of semiconductor manufacturing, etch selectivity between different materials may be used to ensure, e.g., that patterning using masks may be performed, where two materials may be described as “sufficiently etch-selective” if etchants used to etch one material do not substantially etch the other material, and vice versa. In various embodiments, the HM1 material 206 may include materials such as aluminum nitride, aluminum oxide, silicon nitride, or silicon carbon nitride, as long as the HM1 material 206 is sufficiently etch-selective with respect to the M1 material 204. Various mask materials described herein, e.g., the HM1 material 206, may be deposited using a deposition technique such as, but not limited to, spin-coating, dip-coating, ALD, CVD, or PVD.
A thickness of the M1 material 204 (in this case, a dimension measured along the z-axis of the example coordinate system shown in the present drawings) deposited in the process 102 may be substantially equal to a sum of a height of the bottom line to be formed of the M1 material 204 and a height of the bottom via portion of a stacked via to also be formed of the M1 material 204 in later fabrication processes. For example, in some embodiments, the thickness of the M1 material 204 may be between about 20 and 300 nanometers, including all values and ranges therein, e.g., between about 30 and 150 nanometers, or between about 35 and 100 nanometers. The thickness of the HM1 material 206 may be between about 2 and 50 nanometers, including all values and ranges therein, e.g., between about 3 and 30 nanometers, or between about 5 and 20 nanometers.
The method 100 may then proceed with a process 104 that includes patterning the HM1 material deposited in the process 102 to form what may be referred to as a “bottom metal line pattern,” defining shapes and locations of one or more bottom metal lines to be formed of the M1 material deposited in the process 102, and further includes removing the M1 material exposed by the bottom metal line pattern to form one or more bottom metal lines. An IC structure 200B, depicted in
As shown in
In some embodiments, the etches performed in the process 104 to etch, first, the HM1 material 206, and then the M1 material 204 may include anisotropic etches, using etchants in a form of, e.g., chemically active ionized gas (i.e., plasma) using e.g., bromine (Br) and chloride (CI) based chemistries. In some embodiments, during the etches of the process 104, the IC structure may be heated to elevated temperatures, e.g., to temperatures between about room temperature and 200 degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface.
Next, the method 100 may then proceed with a process 106 that includes patterning the bottom metal line pattern of the HM1 material formed in the process 104 to form what may be referred to as a “bottom via portion pattern,” defining shapes and locations of one or more bottom portions of future stacked vias, the bottom portions to be formed of the M1 material under the lines 203 formed in the process 104. The process 106 further includes recessing (i.e., partially removing) the M1 material exposed by the bottom via portion pattern to form one or more bottom via portions above bottom metal lines, and then removing the remaining portions of the HM1 material.
An IC structure 200C, depicted in
An IC structure 200D, depicted in
An IC structure 200E, depicted in
As a result of using subtractive patterning of the M1 material 204 to form the bottom metal lines 211 and the bottom via portions 209, as described above, the bottom via portions 209 may be self-aligned to the corresponding bottom metal lines 211 (i.e., of the bottom metal lines 211 from which the bottom via portions 209 are protruding), in a direction of the y-axis of the example coordinate system shown, wherein in a direction of the x-axis of the example coordinate system the bottom via portions 209 are just defined by the lithography of the HM1 material 206 when the islands 207 were formed. This may be explained with reference to one of the bottom via portions 209 for which first, second, third, and fourth side faces are labeled in
The method 100 may then proceed with a process 108 that includes depositing a first dielectric (D1) material, depositing a second hardmask (HM2) material, patterning the HM2 material to form a top metal line pattern, and recessing (i.e., partially removing) the D1 material exposed by the top metal line pattern of the HM2 material to form one or more top line openings.
An IC structure 200F, depicted in
A thickness of the D1 material 208 (in this case, a dimension measured along the z-axis of the example coordinate system shown in the present drawings) deposited as a result of the process 108 may be substantially equal to a sum of a height of the top line to be formed in a later fabrication process, a height of the top via portion of the stacked via also to be formed in a later fabrication process, and, if the thickness of the D1 material 208 is measured from the top of the bottom metal line 211, a height of the bottom via portion 209 of the stacked via. If the thickness of the D1 material 208 is measured from the top of the bottom via portion 209, then the thickness may be substantially equal to the sum of the height of the top line to be formed in a later fabrication process and the height of the top via portion of the stacked via also to be formed in a later fabrication process. For example, in some embodiments, the thickness of the D1 material 208, measured from the top of the bottom via portion(s) 209, may be between about 20 and 300 nanometers, including all values and ranges therein, e.g., between about 30 and 150 nanometers, or between about 50 and 100 nanometers.
An IC structure 200G, depicted in
An IC structure 200H, depicted in
An IC structure 2001, depicted in
The method 100 may then proceed with a process 110 that includes depositing a second dielectric (D2) material, depositing a third hardmask (HM3) material, patterning the HM3 material to form a top via portion pattern, and removing the D2 material exposed by the top via portion pattern of the HM3 material as well as by the top metal line pattern of the HM2 material to form one or more intermediate top via portion openings.
An IC structure 200J, depicted in
An IC structure 200K, depicted in
An IC structure 200L, depicted in
The method 100 may then proceed with a process 112 that includes removing the D1 material exposed by the intermediate top via portion openings 221 formed in the process 110 (i.e., exposed by the openings 219 of the top via portion pattern of the HM3 material 214 and by the openings 213 of the top metal line pattern of the HM2 material 210) to form top via portion openings. An IC structure 200M, depicted in
Next, the method 100 may include a process 114 that includes remove all of the HM3 material 214 and all of the D2 material 212. Optionally, the HM2 material 210 may be removed as well in the process 114. An IC structure 200N, depicted in
The method 100 may conclude with a process 116 that includes depositing a second electrically conductive (M2) material into the openings 217 and 223 and polishing the M2 material to expose the D1 material.
An IC structure 2000, depicted in
An IC structure 200P, depicted in
Faces F1b-F4b for one example bottom via portion 209 are labeled in the top-down view of
As a result of using Damascene processing as described above to form the top metal lines 227 and the top via portions 229, the top via portions 229 may be self-aligned to the corresponding top metal lines 227 (i.e., of the top metal lines 227 from which the openings 223 for the top via portions 229 were formed), in a direction of the x-axis of the example coordinate system shown, wherein in a direction of the y-axis of the example coordinate system the top via portions 229 are just defined by the lithography of the HM3 material 214 when the openings 219 were formed as shown in
The principles described above are also illustrated in
Variations and Implementations
The IC structures illustrated in and described with reference to
For example, although not specifically shown in the present drawings, in further embodiments, one or more barrier materials may be implemented around portions of electrically conductive materials (e.g., enclosing sidewalls of any of the bottom metal lines 211, the top metal lines 227, the bottom via portions 209, and the top via portions 229), to prevent diffusion of the electrically conductive material of these portions to the surrounding dielectric/insulating materials.
In another example, although also not specifically shown in the present drawings, in further embodiments, there may be a layer of interface material between the M1 material 204 of the bottom via portion 209 and the M2 material 216 of the top via portion 229.
In yet another example, although
Example Devices
The IC structures with one or more stacked vias with bottom portions formed using subtractive patterning, disclosed herein, may be included in any suitable electronic device. For example, in various embodiments, the IC structures as described herein may be a part of at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communications device.
The package substrate 2252 may be formed of a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, etc.), and may have conductive pathways extending through the dielectric material between the face 2272 and the face 2274, or between different locations on the face 2272, and/or between different locations on the face 2274.
The package substrate 2252 may include conductive contacts 2263 that are coupled to conductive pathways 2262 through the package substrate 2252, allowing circuitry within the dies 2256 and/or the interposer 2257 to electrically couple to various ones of the conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).
The IC package 2200 may include an interposer 2257 coupled to the package substrate 2252 via conductive contacts 2261 of the interposer 2257, first-level interconnects 2265, and the conductive contacts 2263 of the package substrate 2252. The first-level interconnects 2265 illustrated in
The IC package 2200 may include one or more dies 2256 coupled to the interposer 2257 via conductive contacts 2254 of the dies 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) through the interposer 2257, allowing circuitry within the dies 2256 to electrically couple to various ones of the conductive contacts 2261 (or to other devices included in the interposer 2257, not shown). The first-level interconnects 2258 illustrated in
In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257 around the first-level interconnects 2265, and a mold compound 2268 may be disposed around the dies 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the mold compound 2268. Example materials that may be used for the underfill material 2266 and the mold compound 2268 are epoxy mold materials, as suitable. Second-level interconnects 2270 may be coupled to the conductive contacts 2264. The second-level interconnects 2270 illustrated in
The dies 2256 may take the form of any of the embodiments of the die 2002 discussed herein (e.g., may include any of the embodiments of the IC structures with one or more stacked vias with bottom portions formed using subtractive patterning as described herein). In embodiments in which the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry to perform any desired functionality. For example, one or more of the dies 2256 may be logic dies (e.g., silicon-based dies), and one or more of the dies 2256 may be memory dies (e.g., high bandwidth memory). In some embodiments, any of the dies 2256 may include one or more IC structures with one or more stacked vias with bottom portions formed using subtractive patterning as discussed above; in some embodiments, at least some of the dies 2256 may not include any stacked vias with bottom portions formed using subtractive patterning.
The IC package 2200 illustrated in
In some embodiments, the circuit board 2302 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 2302. In other embodiments, the circuit board 2302 may be a non-PCB substrate.
The IC device assembly 2300 illustrated in
The package-on-interposer structure 2336 may include an IC package 2320 coupled to an interposer 2304 by coupling components 2318. The coupling components 2318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 2316. The IC package 2320 may be or include, for example, a die (the die 2002 of FIG. 5B), an IC device, or any other suitable component. In particular, the IC package 2320 may include one or more stacked vias with bottom portions formed using subtractive patterning as described herein. Although a single IC package 2320 is shown in
The interposer 2304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 2304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 2304 may include any number of metal lines 2310, vias 2308, and through-silicon vias (TSVs) 2306. The interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 2304. The package-on-interposer structure 2336 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 2300 may include an IC package 2324 coupled to the first face 2340 of the circuit board 2302 by coupling components 2322. The coupling components 2322 may take the form of any of the embodiments discussed above with reference to the coupling components 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to the IC package 2320.
The IC device assembly 2300 illustrated in
A number of components are illustrated in
Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in
The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 2402 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 2404 may include memory that shares a die with the processing device 2402.
In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured for managing wireless communications for the transfer of data to and from the computing device 2400. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication chip 2412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 2412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 2412 may operate in accordance with other wireless protocols in other embodiments. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 2412 may include multiple communication chips. For instance, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 2412 may be dedicated to wireless communications, and a second communication chip 2412 may be dedicated to wired communications.
The computing device 2400 may include battery/power circuitry 2414. The battery/power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 2400 to an energy source separate from the computing device 2400 (e.g., AC line power).
The computing device 2400 may include a display device 2406 (or corresponding interface circuitry, as discussed above). The display device 2406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
The computing device 2400 may include an audio output device 2408 (or corresponding interface circuitry, as discussed above). The audio output device 2408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). The GPS device 2416 may be in communication with a satellite-based system and may receive a location of the computing device 2400, as known in the art.
The computing device 2400 may include an other output device 2410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The computing device 2400 may include an other input device 2420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.
The following paragraphs provide various examples of the embodiments disclosed herein.
Example 1 provides an IC structure that includes a support structure (e.g., a support structure 202, shown in the present drawings, e.g., a substrate), a first metallization layer and a second metallization layer, and a via. The first metallization layer and second metallization layer are provided over the support structure, where the first metallization layer includes a bottom electrically conductive line, the second metallization layer includes a top electrically conductive line, and the first metallization layer is between the support structure and the second metallization layer. The via has a bottom via portion coupled to the bottom electrically conductive line and a top via portion coupled to the top electrically conductive line. In such an IC structure, the bottom via portion is self-aligned to the bottom electrically conductive line, and the top via portion is self-aligned to the top electrically conductive line.
Example 2 provides the IC structure according to example 1, where the bottom via portion is self-aligned to the bottom electrically conductive line by having a first face of the bottom via portion (e.g., the face F1b, shown in the present drawings) being substantially in a single plane with a first sidewall of the bottom electrically conductive line (e.g., the sidewall S1b, shown in the present drawings), and having a second face of the bottom via portion being (e.g., the face F2b, shown in the present drawings) substantially in a single plane with a second sidewall of the bottom electrically conductive line (e.g., the sidewall S2b, shown in the present drawings), where the second face of the bottom via portion is opposite the first face of the bottom via portion.
Example 3 provides the IC structure according to example 1, where the bottom via portion is self-aligned to the bottom electrically conductive line by having a first face of the bottom via portion (e.g., the face F1b, shown in the present drawings) being aligned with a first sidewall of the bottom electrically conductive line (e.g., the sidewall S1b, shown in the present drawings), and by having a second face of the bottom via portion (e.g., the face F2b, shown in the present drawings) being aligned with a second sidewall of the bottom electrically conductive line (e.g., the sidewall S2b, shown in the present drawings), where the second face of the bottom via portion is opposite the first face of the bottom via portion.
Example 4 provides the IC structure according to examples 2 or 3, where the first face of the bottom via portion is substantially parallel to the second face of the bottom via portion.
Example 5 provides the IC structure according to any one of examples 1-4, where the top via portion is self-aligned to the top electrically conductive line by: having a third face of the top via portion (e.g., the face F3t, shown in the present drawings) being substantially in a single plane with a first sidewall of the top electrically conductive line (e.g., the sidewall S1t, shown in the present drawings), and having a fourth face of the top via portion (e.g., the face F4t, shown in the present drawings) being substantially in a single plane with a second sidewall of the top electrically conductive line (e.g., the sidewall S2t, shown in the present drawings), where the fourth face of the top via portion is opposite the third face of the top via portion.
Example 6 provides the IC structure according to any one of examples 1-4, where the top via portion is self-aligned to the top electrically conductive line by: having a third face of the top via portion (e.g., the face F3t, shown in the present drawings) being aligned with a first sidewall of the top electrically conductive line (e.g., the sidewall S1t, shown in the present drawings), and having a fourth face of the top via portion (e.g., the face F4t, shown in the present drawings) being aligned with a second sidewall of the top electrically conductive line (e.g., the sidewall S2t, shown in the present drawings), where the fourth face of the top via portion is opposite the third face of the top via portion.
Example 7 provides the IC structure according to example 5 or 6, where the third face of the top via portion is substantially parallel to the fourth face of the top via portion.
Example 8 provides the IC structure according to any one of the preceding examples, where each of the bottom via portion and a top via portion has a first face, a second face, a third face, and a fourth face, where the second face is opposite (i.e., does not share an edge with) the first face, and where the fourth face is opposite the third face (e.g., assuming that, ideally, the via portions have sidewalls substantially perpendicular to the substrate and referring to the example coordinate system shown in the present drawings, the first face is a face in one x-z plane, the second face is a face in another x-z plane, which is at a certain distance (i.e., a width of the bottom electrically conductive line) from the first x-z plane, the third face is a face in one y-z plane, and the fourth face is a face in another y-z plane, which is at a certain distance (i.e., a width of the top electrically conductive line) from the first y-z plane). In such an IC structure, the first face of the bottom via portion is in a single plane with a first sidewall of the bottom electrically conductive line, the second face of the bottom via portion is in a single plane with a second sidewall of the bottom electrically conductive line, the third face of the top via portion is in a single plane with a first sidewall of the top electrically conductive line, and the fourth face of the top via portion being in a single plane with a second sidewall of the top electrically conductive line.
Example 9 provides the IC structure according to example 8, where a distance between the first and second faces of the bottom via portion is smaller than a distance between the first and second faces of the top via portion (see, e.g., the misalignment shown in the cross-sectional side view of
Example 10 provides the IC structure according to example 8 or 9, where a distance between the third and fourth faces of the top via portion is smaller than a distance between the third and fourth faces of the bottom via portion (see, e.g., the misalignment shown in the cross-sectional side view of
Example 11 provides the IC structure according to any one of example 8-10, where each of the first and second faces of the bottom via portion is substantially flat (i.e., each substantially belongs to a single plane).
Example 12 provides the IC structure according to any one of example 8-11, where each of the third and fourth faces of the top via portion is substantially flat.
Example 13 provides an IC structure that includes a support structure, a first metallization layer and a second metallization layer provided over the support structure. The first metallization layer includes a bottom electrically conductive line, the second metallization layer includes a top electrically conductive line, and the first metallization layer is between the support structure and the second metallization layer (i.e., a top electrically conductive line, further away from the support structure than the bottom electrically conductive line). The IC structure further includes a via having a bottom via portion coupled to the bottom electrically conductive line and a top via portion coupled to the top electrically conductive line, where the bottom via portion has a first width at a first distance from the support structure and has a second width at a second distance from the support structure, where the first distance is smaller than the second distance and the second width of the bottom via portion is smaller than the first width of the bottom via portion.
Example 14 provides the IC structure according to example 13, where the top via portion has a first width at a third distance from the support structure and has a second width at a fourth distance from the support structure, where the third distance is smaller than the fourth distance and the first width of the top via portion is smaller than the second width of the top via portion.
Example 15 provides the IC structure according to example 14, where each of the bottom electrically conductive line and the top electrically conductive line has a length, a width, and a height, the length being greater than each of the width and the height, the length of the bottom electrically conductive line is a dimension measured along an x-axis of a coordinate system, the length of the top electrically conductive line is a dimension measured along a y-axis of the coordinate system, the height of each of the bottom electrically conductive line and the top electrically conductive line is a dimension measured along a z-axis of the coordinate system, each of the first width and the second width of the bottom via portion is a dimension measured along a y-z plane of the coordinate system, and each of the first width and the second width of the top via portion is a dimension measured along an x-z plane of the coordinate system.
Example 16 provides the IC structure according to example 15, where each of a cross-section of the bottom via along the y-z plane of the coordinate system and a cross-section of the top via portion along the x-z plane of the coordinate system is substantially a trapezoid, but the trapezoids are inverted with respect to one another.
Example 17 provides the IC structure according to any one of example 13-16, where a first face of the bottom via portion is in a single plane with a first sidewall of the bottom electrically conductive line, and a second face of the bottom via portion is in a single plane with a second sidewall of the bottom electrically conductive line, where the second face of the bottom via portion is opposite the first face of the bottom via portion. Furthermore, a third face of the top via portion is in a single plane with a first sidewall of the top electrically conductive line, and a fourth face of the top via portion is in a single plane with a second sidewall of the top electrically conductive line, where the fourth face of the top via portion is opposite the third face of the top via portion.
Example 18 provides the IC structure according to example 17, where at least one is true: a third face of the bottom via portion is not in a single plane with a first sidewall of the top electrically conductive line, or a fourth face of the bottom via portion is not in a single plane with a second sidewall of the top electrically conductive line, where the fourth face of the bottom via portion is opposite the third face of the bottom via portion, or a first face of the top via portion is not in a single plane with a first sidewall of the bottom electrically conductive line, or a second face of the top via portion is not in a single plane with a second sidewall of the bottom electrically conductive line, where the second face of the top via portion is opposite the first face of the top via portion.
Example 19 provides a method of fabricating an IC structure. The method includes providing, over a support structure (e.g., a substrate, a chip, or a wafer), a stack of a first electrically conductive material (M1) and a first mask material (HM1) so that the first electrically conductive material is between a support structure (e.g., a substrate, a chip, or a wafer) and the first mask material (e.g., see example result in
Example 20 provides the method according to example 19, further including removing excess of the second electrically conductive material so that an upper surface of the second electrically conductive material is substantially flush with an upper surface of the first dielectric material.
Example 21 provides the method according to any one of example 19-20, further including processes for forming the IC structure as the IC structure according to any one of example 1-12.
Example 22 provides the method according to any one of example 19-20, further including processes for forming the IC structure as the IC structure according to any one of example 13-18.
Example 23 provides an IC package that includes an IC die that includes an IC structure according to any one of the preceding examples (e.g., the IC structure according to any one of examples 1-18 and/or an IC structure formed according to the method according to any one of examples 19-22) and a further IC component, coupled to the IC die.
Example 24 provides the IC package according to example 23, where the further component is one of a package substrate, a flexible substrate, or an interposer.
Example 25 provides the IC package according to examples 23 or 24, where the further component is coupled to the IC die via one or more first-level interconnects.
Example 26 provides the IC package according to example 25, where the one or more first-level interconnects include one or more solder bumps, solder posts, or bond wires.
Example 27 provides an electronic device that includes a circuit board; and an IC die coupled to the circuit board, where the IC die includes one or more of: 1) one or more of the IC structures according to any one of example 1-18, 2) one or more of the IC structures formed according to the method according to any one of example 19-22, and 3) one or more of IC packages according to any one of the preceding examples (e.g., each IC package may be an IC package according to any one of examples 23-26).
Example 28 provides the electronic device according to example 27, where the electronic device is a wearable electronic device (e.g., a smart watch) or handheld electronic device (e.g., a mobile phone).
Example 29 provides the electronic device according to examples 27 or 28, where the electronic device is a server processor. Example 30 provides the electronic device according to examples 27 or 28, where the electronic device is a motherboard.
Example 31 provides the electronic device according to any one of examples 27-30, where the electronic device further includes one or more communication chips and an antenna.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.