Anshul Gupta

Person

Leuven, BE

People

Patents Grantslast 30 patents

Information Patent Grant
Method of producing a gate cut in a semiconductor component
- Patent number 12,154,830
- Issue date Nov 26, 2024
- Imec VZW
- Gaspard Hiblot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a buried metal line
- Patent number 11,335,597
- Issue date May 17, 2022
- Imec VZW
- Eugenio Dentoni Litta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for connecting a buried interconnect rail and a semiconducto...
- Patent number 10,957,575
- Issue date Mar 23, 2021
- Imec VZW
- Dmitry Yakimets
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Integrated Circuit Device and a Method for Forming the Same
- Publication number 20240203994
- Publication date Jun 20, 2024
- IMEC vzw
- Anshul Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming an Interconnection Structure
- Publication number 20240170328
- Publication date May 23, 2024
- IMEC vzw
- Anshul Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUPERCONDUCTIVE INTERCONNECT STRUCTURE
- Publication number 20240038589
- Publication date Feb 1, 2024
- IMEC vzw
- Anna Yurievna HERR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Buried Metal Line in a Semiconductor Substrate
- Publication number 20240006228
- Publication date Jan 4, 2024
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF PRODUCING A GATE CUT IN A SEMICONDUCTOR COMPONENT
- Publication number 20220238388
- Publication date Jul 28, 2022
- IMEC vzw
- Gaspard HIBLOT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Buried Metal Line
- Publication number 20210035860
- Publication date Feb 4, 2021
- IMEC vzw
- Eugenio Dentoni Litta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a Buried Metal Line in a Semiconductor Substrate
- Publication number 20210028059
- Publication date Jan 28, 2021
- IMEC vzw
- Boon Teik Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR CONNECTING A BURIED INTERCONNECT RAIL AND A SEMICONDUCTO...
- Publication number 20200203210
- Publication date Jun 25, 2020
- IMEC vzw
- Dmitry Yakimets
- H01 - BASIC ELECTRIC ELEMENTS

Anshul Gupta

Person

Patents Grantslast 30 patents

Method of producing a gate cut in a semiconductor component

Method for forming a buried metal line

Method for connecting a buried interconnect rail and a semiconducto...

Patents Applicationslast 30 patents

Integrated Circuit Device and a Method for Forming the Same

Method for Forming an Interconnection Structure

SUPERCONDUCTIVE INTERCONNECT STRUCTURE

Method for Forming a Buried Metal Line in a Semiconductor Substrate

METHOD OF PRODUCING A GATE CUT IN A SEMICONDUCTOR COMPONENT

Method for Forming a Buried Metal Line

Method for Forming a Buried Metal Line in a Semiconductor Substrate

METHOD FOR CONNECTING A BURIED INTERCONNECT RAIL AND A SEMICONDUCTO...