Patent Application
20240170328
The present application is a non-provisional patent application claiming priority to European Patent Application No. 22208458.4, filed on Nov. 21, 2022, the contents of which are hereby incorporated by reference.
The present disclosure relates to a method for forming an interconnection structure.
Some modern circuit fabrication processes include forming electrical interconnection structures for interconnecting semiconductor devices in a functioning circuit, e.g. in the back-end-of-line (BEOL). An interconnection structure may include one or more interconnection levels or tiers, which are formed above the substrate supporting the active device regions. An interconnection level includes horizontal conductive paths or lines arranged in an insulating material layer. Conductive lines of different interconnection levels may be interconnected by conductive vias extending vertically through the insulating layers.
A conventional approach for forming an interconnection level is the “dual damascene process.” According to this approach, horizontally extending trenches are etched in the insulating layer. Further, vertically extending via holes are formed in the insulating layer. Thereafter the trenches and via holes are simultaneously filled with a conductive material to form conductive lines in the trenches and conductive vias in the via holes. The process may be repeated to form a stack of interconnection levels.
Another approach for forming an interconnection level is to directly etch metal lines in a metal layer using e.g. single-patterning or multi-patterning techniques such as lithography and etching, self-aligned double patterning (SADP), or quadruple patterning (SAQP). Vias may be formed using subtractive etching of the patterned metal lines, wherein vias may be defined by non-recessed portions of the metal lines. Compared to the dual damascene process, a direct metal etch approach may facilitate interconnection level fabrication at more aggressive line pitches by avoiding challenges related to reliably filling narrow trenches with metal, among others.
In some cases it would be desirable to combine metal lines of different heights in a same interconnection level. However, current direct metal etch approaches are lacking in terms of ability to efficiently and reliably form an interconnection level with hybrid-height metal lines.
In light of the above, this disclosure includes a method for forming an interconnection structure allowing forming of an interconnection level comprising metal lines of differing heights.
According to an aspect there is provided a method for forming an interconnection structure, comprising:
The method according to the present aspect can involve forming of an interconnection structure comprising hybrid-height metal features, i.e. metal features of different heights. In some embodiments, the metal features may be metal lines, wherein hybrid-height metal lines, i.e. metal lines of different heights, may be formed. The method is however not so limited but may also be used to form metal features in the form of pillars or metal features with arbitrary 2D layouts, exclusively or in combination with metal lines.
More specifically, the method allows forming of two consecutive interconnection levels, a lower and an upper interconnection level, wherein the set of lower metal features are arranged in the lower interconnection level, the set of upper metal features are arranged in the upper interconnection level, and the stacked metal features are arranged to span the lower and upper interconnection levels. It is hereby to understood that the first portion of the second metal layer pattern overlies and is formed in electrical contact with the second portion of the first metal layer pattern.
The hybrid-height metal feature interconnection structure is enabled by the stacking of the first and second metal layer patterns which subsequently are etched using the mask pattern of the mask material. This is in contrast to a conventional direct metal patterning approach wherein metal features (e.g. metal lines) are patterned in a single blanket-deposited metal layer.
A potential benefit of the present method is that metal features of the first height, metal features of the second height, and metal features of the third height may be interleaved with each other. For instance, a subset of the stacked metal features (e.g. lines) may be formed between a subset of the lower metal features (e.g. lines) and a subset of the upper metal features (e.g. lines). As further may be appreciated, the metal features may be formed in a staggered fashion in the sense that the lower metal features and the upper metal features may be arranged at different vertical levels over the substrate.
The term “covering the first/second dielectric layer pattern with metal” as used herein means that a first/second metal layer is formed to cover and surround the first/second dielectric layer pattern. The first/second metal layer is subsequently planarized to form the first/second metal layer pattern. The metal may be deposited on top of (e.g. in direct contact with) the first/second dielectric layer pattern (and in the case of the second metal layer pattern in direct contact with the first metal layer pattern). The (first/second) metal layer may each be formed of a single metal layer or a stack of metal (sub-)layers of different metals, for instance a stack of a metal liner (sub-)layer and a metal fill (sub-)layer.
Relative spatial terms such as “upper,” “lower,” “top,” “bottom,” and “stacked on top of” are herein to be understood as denoting locations or orientations within a frame of reference relative to the substrate. In particular, the terms may be understood as locations relative a normal direction to a main surface or main plane of extension of the substrate (equivalently a vertical direction). Conversely, terms such as “lateral” and “horizontal” are to be understood as locations or orientations parallel to the substrate, i.e. parallel to the main surface/main plane of extension of the substrate.
The term “height” as used herein accordingly denotes a dimension as seen along the vertical direction. Also the term “thickness” is to be understood in this sense unless stated otherwise.
The term “planarizing” (e.g. as in “planarizing the metal”) as used herein denotes subjecting an initial surface (e.g. an upper surface of deposited metal or layer) to a planarization process to produce a planar surface (wherein the surface initially may have a varying topography). For example, the act of “planarizing” may comprise chemical mechanical polishing (CMP).
The term “using a feature as an etch mask” (where the “feature” refers to a feature such as a layer or a line) as used herein means that one or more underlying layers are etched while the feature counteracts etching of portions of the underlaying layer(s) masked by the feature (i.e. portions overlapped or covered by the feature).
In some embodiments, the first sub-pattern may further be transferred into the portion of the second dielectric layer pattern to form a set of dielectric features, wherein the lower set of metal features are capped by the set of dielectric features. This may facilitate connecting the lower metal features with vias by enabling forming of via holes self-aligned to the lower metal features (by selective etching of the dielectric features). Various embodiments for via formation are further set out in the following.
In some embodiments, forming one of the first and the second dielectric layer pattern may comprise forming a dielectric layer and patterning a set of openings in the dielectric layer, and wherein forming the other one of the first and second dielectric layer pattern may comprise forming a dielectric layer and patterning a set of dielectric blocks in the dielectric layer. Hence, a set of openings may be patterned in the first dielectric layer (e.g. using a lithography and etching process) and a set of dielectrics blocks may be patterned in the second dielectric layer (e.g. using a lithography and etching process), or vice versa.
The term “openings” is hereby used to refer to cavities etched through the first or second dielectric layer. The first/second metal layer pattern may accordingly fill the set of openings in the first/second dielectric layer. The first/second metal layer pattern may accordingly be defined by a set of first/second metal layer pattern parts, each pattern part formed in a respective opening in the first/second dielectric layer pattern.
The dielectric blocking pattern defines regions in which no stacked metal features are to be formed. The first/second metal layer pattern may surround the dielectric blocks of the first/second dielectric layer pattern.
The mask material of the mask pattern may be a hard mask material, e.g. a dielectric hard mask material.
Forming the mask pattern may comprise forming a mask layer of the mask material over the second dielectric layer pattern and the second metal layer pattern and patterning the mask layer to form the mask pattern.
In some embodiments, the method may further comprise depositing an interlayer dielectric to embed and cover the sets of metal lines and the mask line pattern of the mask material, and planarizing the interlayer dielectric to expose an upper surface of mask line pattern.
The upper surface of the mask line pattern may be used for end point detection for the planarizing (i.e. planarization process e.g. CMP) of the interlayer dielectric. In other words, the planarizing of the interlayer dielectric may be stopped in response to detecting the upper surface of the mask line pattern.
The mask pattern may comprise a pattern of mask lines of the mask material. This enables forming of metal features in the form of metal lines (e.g. lower, upper, and stacked metal lines).
The mask line pattern may comprise a grating of lines of the mask material. This enables a relatively large area of mask material (e.g. hard mask material) for end point detection for the planarization process applied to the interlayer dielectric.
In some embodiments, the method may further comprise method steps for forming metal vias on top of the lower, upper, and/or stacked metal features (e.g. metal lines).
The method may comprise patterning a first via hole thereby exposing an upper surface of a first lower metal feature, the first via hole extending through a first mask feature of the mask pattern overlying the first lower metal feature (and a first dielectric feature overlying/capping the first lower metal feature); and forming a first metal via in the first via hole.
The method may additionally or alternatively comprise patterning a second via hole thereby exposing an upper surface of a first stacked metal feature and extending through a second mask feature of the mask pattern overlying the first stacked metal feature; and forming a second metal via in the second via hole.
The method may additionally or alternatively comprise patterning a third via hole thereby exposing an upper surface of a first upper metal feature and extending through a third mask feature of the mask pattern overlying the first upper metal feature; and forming a third metal via in the third via hole.
In each of these cases, via formation (e.g. first, second, or third) may be achieved without any metal etch back but by forming respective via holes (in which metal vias are subsequently formed). The mask feature of the mask pattern (as they overlie/overlap the underlying metal lines) facilitates aligning the via holes with the respective metal features.
Since the upper surfaces of the upper and stacked metal feature may be located at a same level above the substrate, the second and third via holes and metal vias may be of relatively low aspect ratio (LAR). The first via hole and metal via may have a relatively high aspect ratio (HAR) as it extends through the upper level to reach the upper surface of the lower metal feature.
Each one of the first, second, and third via holes may be patterned simultaneously, e.g. using a same via mask layer as etch mask.
Forming the first, second, and/or third via hole may comprise etching the mask material selectively to the interlayer dielectric. This enables the via holes to be formed to in a self-aligned manner to the metal lines.
Forming the first via hole may further comprise etching a dielectric material of the first dielectric feature capping the first lower metal feature selectively to the interlayer dielectric. Hence a lower portion of the first via hole may be formed in a self-aligned manner.
In some embodiments, the method may further comprise forming a metal liner (which may be denoted “upper metal liner”) after forming the second dielectric layer pattern and the second metal layer pattern and subsequently forming the mask pattern on the metal liner. The (upper) metal liner may serve as a metal adhesion layer, facilitating adhesion of the mask material of the mask pattern, in particular of the portion(s) of the mask pattern overlying the second metal layer pattern. This may further increase the flexibility of the method with respect to material choices for the mask material and the second metal layer pattern.
The (upper) metal liner/adhesion layer may be deposited selectively on an upper surface of the second metal layer pattern. The metal liner may hence be formed selectively on the surfaces where improved adhesion may provide the most benefit. Additionally, by a selective deposition, sandwiching of metal liner portions between the second dielectric layer pattern and the mask pattern, which could create line to line shorts if not removed, may thus be avoided.
In embodiments comprising forming the (upper) metal liner, each upper metal feature and each stacked metal feature may comprise a respective thickness portion of the metal liner. Accordingly, each upper metal feature may comprise a thickness portion of the second metal layer pattern and a thickness portion of the metal liner, and each stacked metal feature may comprise a thickness portion of the first metal layer pattern, a thickness portion of the metal liner, and a thickness portion of the second metal layer pattern.
In some embodiments, the method may further comprise forming a metal liner (which may be denoted “lower metal liner”) after forming the first dielectric layer pattern and the first metal layer pattern and subsequently forming the second dielectric layer pattern on the metal liner. The (lower) metal liner may serve as a metal adhesion layer, facilitating adhesion of the second dielectric layer pattern, in particular of the portion(s) of the second dielectric layer pattern overlying the first metal layer pattern. This may further increase the flexibility of the method with respect to material choices for the second dielectric layer and the first metal layer pattern.
The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.
All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.
Methods for forming an interconnection structure, suitable for instance for a semiconductor device, will now be described with reference to the figures. The methods will be described in connection with forming interconnection levels exemplified in the figures as a bottom interconnection level. It is however noted that the methods herein have a more general applicability and may be used for forming any interconnection level of a stack of interconnection levels of an interconnection structure. The methods herein allows forming of an interconnection structure comprising two consecutive levels, a lower and an upper level, wherein the interconnection structure comprises a set of lower metal lines in the lower level, a set of upper metal lines in the upper level, and a set of stacked metal lines spanning the lower and upper levels. Using a conventional notation for interconnection levels, the lower level may be denoted MX and the upper level may be denoted MX+1. While the illustrated examples refer to metal features in the shape of metal lines, it is to be noted that the method has a more general applicability and may be used to form hybrid-height metal features with arbitrary 2D layout, or hybrid-height metal pillars.
A first dielectric layer 108 is formed over the substrate 102, more specifically on top of the insulating layer structure (e.g. interlayer dielectric 104 and the dielectric capping layer 106). The first dielectric layer 108 may, like the interlayer dielectric 104, be formed of SiO2 or of another low-k insulating material (e.g. an oxide) suitable as interlayer dielectric in an interconnection structure. The first dielectric layer 108 may be formed using conventional deposition techniques such as chemical vapor deposition (CVD), flowable-CVD, or physical vapor deposition (PVD).
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While not shown in the figures, it is to be understood that prior to forming the first dielectric layer 108, a pattern of metal vias may be formed in the insulating layer structure, on top of conductive structures (e.g. contact structures or metal lines) embedded therein, to enable an electrical connection to the metal lines that are to be formed in the lower level (e.g. MX). The metal vias may e.g. be formed by patterning via holes in the insulating layer structure (e.g. through interlayer dielectric 104 and the dielectric capping layer 106) and filling the same with metal. A top surface of the metal vias may then be exposed in set of openings 112 patterned in the first dielectric layer 108 such that the first metal layer 118 may be formed in electrical contact with the metal vias. It is also possible to pattern via holes in the insulating layer structure after patterning the first dielectric layer 108, e.g. by etching via holes through the first dielectric layer 108 and the dielectric capping layer 106 from the set openings 112 patterned in the first dielectric layer 108. The via holes may then be filled by the first metal layer 118.
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A mask layer 128 has further been formed on top of the second dielectric layer 126 and patterned to define a set of mask blocks (of which
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Accordingly, at the stage of the method depicted in
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The illustrated example shows a single discrete metal pattern part of the first metal layer pattern 122 within the opening 116 in the first dielectric layer pattern 114. However, it is to be understood that the first metal layer pattern 122 may comprise a set of plural discrete metal pattern parts, each metal pattern part formed in a respective one of a set of plural openings 116 in the first dielectric layer pattern 114. Each metal pattern that is part of the first metal layer pattern 122 may be formed with a first horizontal dimension (e.g. along the X direction) such that at least one lower metal line may be patterned therein, and/or such that at least a lower portion of a stacked metal line may be patterned therein. For example, the first horizontal dimension of a metal pattern part of the first metal layer pattern 122 may be at least N*p, where N≥ 1 and p is the (minimum) pitch of the pattern of metal lines that is to be formed in the first metal layer pattern 122. A second horizontal dimension (e.g. along the Y direction) of each metal pattern that is part of the first metal layer pattern 122 may define a maximum length of a lower or a stacked metal line which may be patterned therein.
Correspondingly, the illustrated example shows a single discrete dielectric block of the second dielectric layer pattern 130. However, it is to be understood that the second dielectric layer pattern 130 may comprise a set of multiple discrete dielectric blocks. Each dielectric block of the second dielectric layer pattern 130 may define a region in which no upper metal lines are to be formed.
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An etch mask 142 defining a pattern of lines has been formed over the mask material layer 140. The pattern of lines of the etch mask 142 may be formed using single-patterning or multi-patterning techniques, such as lithography (e.g. Extreme Ultraviolet Lithography) and etching, or pitch splitting techniques such as SADP or SAQP. In the illustrated example, the etch mask 142 is formed to define a grating of lines regularly spaced apart. The method is however not so limited but it is also possible to form lines with different spacing and/or of different lengths. Further, the method is not limited to lines parallel along their entire lengths (i.e. unidirectional lines). For example, the lines of the pattern (or subsets thereof) may comprise portions extending along the X-direction and portions extending along the Y-direction. Variations in the line pattern may for example be introduced by forming cuts in the pattern of lines of the etch mask 142 prior to being transferred into the mask material layer 140.
While in the depicted example, the metal liner layer 124 (see
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In the illustrated example, both lower metal lines 150 and lower line portions 153 are formed (in part) in a same discrete part of the first metal layer pattern 122. This is however merely an example and it is also possible to form e.g. only lower metal lines 150 in a first discrete part of the first metal layer pattern 122 and only lower line portions 153 in another discrete part of the first metal layer pattern 122. Correspondingly, it is possible to form only upper metal lines 156 in a first discrete part of the second metal layer pattern 136 and only upper line portions 154 in another discrete part of the first metal layer pattern 122. It is further to be noted that the dielectric lines 148, the lower metal lines 150, stacked metal lines 152, upper metal lines 156 shown in
As per the illustrated example, the metal liner layer 124 may be used as an etch stop layer for the transfer of the first sub-pattern into the second dielectric layer pattern 130 and also for the transfer of the second and third sub-patterns into the second metal layer pattern 136. Furthermore, the dielectric capping layer 106 may be used as an etch stop layer for the transfer of the first, second, and third sub-pattern into the first metal layer pattern 122. As a non-limiting example for a layer stack comprising the dielectric capping layer 106 of SiN, a first metal layer pattern 122 and a second metal layer pattern 136 comprising a Ru fill metal, a second dielectric layer pattern 130 of SiN, a mask line pattern of SiN, and the metal liner layer 119, the metal liner layer 124, the metal liner layer 133, the metal liner layer 138 of TiN, the etching process may after patterning the mask material layer 140 to form the mask line pattern proceed as follows:
As may be appreciated by the skilled person, the etching process used for the pattern transfer may comprise a number of successive etch steps comprising different chemistries selected in accordance with the specific material that is to be etched.
In the illustrated example, a set of openings 112 is patterned in the first dielectric layer 108 and a set of dielectrics blocks (i.e., the second dielectric layer pattern 130) is patterned in the second dielectric layer 126. However, it is also possible to pattern a set of dielectric blocks (corresponding to the second dielectric layer pattern 130) in the first dielectric layer 108 and a set of openings (corresponding to openings 112) in the second dielectric layer 126. The combination of openings in one of the dielectric layers and blocks in the other dielectric layer may be a convenient choice specifically for metal line patterning; the blocks may be used to define sub-regions in which no stacked metal lines are to be formed, within a densely populated region/pattern of upper metal lines (in case the blocks are patterned in the mask layer 128) or lower metal lines (in case the blocks are patterned in the first dielectric layer 108), and the openings may be used to define sub-regions in which lower metal line portions (in case the openings are patterned in the first dielectric layer 108) or upper metal line portions of stacked metal lines are to be formed. As may be appreciated, the relative populations of upper metal lines, stacked metal lines, and lower metal lines may be controlled via the relative footprints and the overlap of the openings and the blocks (more generally via the relative footprints and the overlap of the first dielectric layer pattern and the second dielectric layer pattern).
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More specifically, as shown, a first via hole 172 exposing an upper surface of a first lower metal line 150a is patterned by etching from the via opening 162. The first via hole 172 extends through a first mask line of the mask line pattern 144 overlying the first lower metal line 150a, and a first dielectric line of the set of dielectric lines 148 capping the first lower metal line 150a (and the metal liner layer 138 and/or the metal liner layer 138124 if present).
A second via hole 174 exposing an upper surface of a stacked metal line 152 is patterned by etching from the via opening 164. The second via hole 174 extends through a second mask line of the mask line pattern 144 overlying the stacked metal line 152 (and the metal liner layer 138 if present).
A third via hole 176 exposing an upper surface of a first upper metal line 156a is patterned by etching from the third via opening 166. The third via hole 176 extends through a third mask line of the mask line pattern 144 overlying the first upper metal line 156a (and the metal liner layer 138 if present).
The etching process used for the via hole patterning may comprise a number of successive etch steps comprising different chemistries selected in accordance with the specific material that is to be etched.
The mask material of the first, second, and third dielectric lines of the mask line pattern 144 may be etched selectively to the interlayer dielectric 158, wherein the via holes 172, the via holes 174, and the via holes 176 may be self-aligned with the first lower metal lines 150a, the stacked metal lines 152, and the first upper metal line 156a underneath. Forming the first via hole may further comprise etching the dielectric material of the first dielectric line capping the first lower metal line 150a selectively to the interlayer dielectric 158. Hence also a lower portion of the first via hole 172 may be formed in a self-aligned manner with respect to the first lower metal line 150a. Etching processes and chemistries for etching e.g. conventional dielectrics and dielectric hard mask materials (e.g. SiN, AlN, AlOx, or SiOC) selectively to interlayer dielectrics (e.g. SiO2) are per se known in the art.
The etching process (e.g. each of the etch steps thereof) may further be adapted to not appreciably etch the fill metal of the lower metal lines 150, the stacked metal lines 152, and the upper metal lines 156. In other words, the lower metal lines 150, the stacked metal lines 152, and the upper metal lines 156 may be used as an etch stop layer for the etching process. Depending on presence of the metal liner layer 124 and/or the metal liner layer 138, the etching process may comprise an etch step for opening the metal liner layer 138 (to form the via holes 172, the via holes 174, and the via holes 176) and/or an etch step for opening the metal liner layer 124 (to form the via hole 172). These etch steps may be selective to the metal liner layer 138 or the metal liner layer 124 to not appreciably etch the surrounding dielectric and the mask layer 160.
While in the illustrated example, the first via holes 172, the second via holes 174, and the third via holes 176 are patterned simultaneously using the mask layer 160 as etch mask, it is also possible to pattern the first via holes 172, the second via holes 174, and the third via holes 176 sequentially using different etch masks. For instance, the first via holes 172 may be patterned using a first lithography and etching process and the second via holes 174 and the third via holes 176 may be patterned sequentially using a second and a third lithography and etching process, respectively, or simultaneously using a (common) second lithography and etching process.
After forming the first via holes 172, the second via holes 174, and the third via holes 176, the mask layer 160 may be removed and the via formation may be completed by filling the via holes 172, the via holes 174, and the via holes 176 with metal. Overburden metal may be removed by planarization. The metal via formed in the first via hole 172 may form a HAR via, while the metal vias in the second via holes 174 and the third via holes 176 may form LAR vias.
The method may then proceed with forming metal lines of a further interconnection level (e.g. MX+2), for instance by repeating the method steps described above, or using a conventional damascene-style process.
In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.
While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.
| Number | Date | Country | Kind |
|---|---|---|---|
| 22208458.4 | Nov 2022 | EP | regional |
