Anthony G. Aipperspach

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
On-chip diagnostic circuitry monitoring multiple cycles of signal s...
- Patent number 10,311,966
- Issue date Jun 4, 2019
- International Business Machines Corporation
- Anthony G. Aipperspach
- G01 - MEASURING TESTING
Information Patent Grant
Detecting maximum voltage between multiple power supplies for memor...
- Patent number 9,715,905
- Issue date Jul 25, 2017
- International Business Machines Corporation
- Anthony G. Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Level-shifting latch
- Patent number 9,712,170
- Issue date Jul 18, 2017
- International Bueinss Machines Corporation
- Anthony G. Aipperspach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electrostatic discharge protection device with power management
- Patent number 9,583,938
- Issue date Feb 28, 2017
- International Business Machines Corporation
- Anthony G. Aipperspach
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Level-shifting latch
- Patent number 9,553,584
- Issue date Jan 24, 2017
- International Business Machines Corporation
- Anthony G. Aipperspach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electrostatic discharge protection device with power management
- Patent number 9,496,712
- Issue date Nov 15, 2016
- International Business Machines Corporation
- Anthony G. Aipperspach
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Implementing enhanced performance dynamic evaluation circuit by com...
- Patent number 9,424,389
- Issue date Aug 23, 2016
- International Business Machines Corporation
- Anthony G. Aipperspach
- G01 - MEASURING TESTING
Information Patent Grant
Implementing enhanced performance dynamic evaluation circuit by com...
- Patent number 9,396,303
- Issue date Jul 19, 2016
- International Business Machines Corporation
- Anthony G. Aipperspach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing low power, single master-slave elastic buffer
- Patent number 8,643,421
- Issue date Feb 4, 2014
- International Business Machines Corporation
- Anthony G. Aipperspach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Implementing integrated circuit mixed double density and high perfo...
- Patent number 8,513,815
- Issue date Aug 20, 2013
- International Business Machines Corporation
- Anthony G. Aipperspach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implementing precise resistance measurement for 2D array efuse bit...
- Patent number 7,764,531
- Issue date Jul 27, 2010
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for implementing eFuse sense amplifier testing without bl...
- Patent number 7,733,722
- Issue date Jun 8, 2010
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for implementing enhanced eFuse sense circuit
- Patent number 7,729,188
- Issue date Jun 1, 2010
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for implementing eFuse sense amplifier verification
- Patent number 7,725,844
- Issue date May 25, 2010
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing Efuse sense amplifier testing without blowing the Efuse
- Patent number 7,689,950
- Issue date Mar 30, 2010
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for testing a memory
- Patent number 7,562,267
- Issue date Jul 14, 2009
- International Business Machines Corporation
- Anthony G. Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Asymmetrical random access memory cell, and a memory comprising asy...
- Patent number 7,535,750
- Issue date May 19, 2009
- International Business Machines Corporation
- Otto Wagner
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically programmable fuse sense circuit
- Patent number 7,532,057
- Issue date May 12, 2009
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrically programmable fuse sense circuit
- Patent number 7,528,646
- Issue date May 5, 2009
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for predicting and/or calibrating memory yields
- Patent number 7,506,282
- Issue date Mar 17, 2009
- International Business Machines Corporation
- Chad A. Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for implementing eFuse sense amplifier testing without blowi...
- Patent number 7,489,572
- Issue date Feb 10, 2009
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay mechanism for unbalanced read/write paths in domino SRAM arrays
- Patent number 7,400,550
- Issue date Jul 15, 2008
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulse-width limited chip clock design
- Patent number 7,318,209
- Issue date Jan 8, 2008
- International Business Machines Corporation
- Anthony Gus Aipperspach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for accessing memory
- Patent number 7,289,370
- Issue date Oct 30, 2007
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Simplified method for limiting clock pulse width
- Patent number 7,242,233
- Issue date Jul 10, 2007
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for accessing memory
- Patent number 7,239,559
- Issue date Jul 3, 2007
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Glitch protect valid cell and method for maintaining a desired stat...
- Patent number 7,224,594
- Issue date May 29, 2007
- International Business Machines
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Grant
Array redundancy supporting multiple independent repairs
- Patent number 7,206,236
- Issue date Apr 17, 2007
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic latching logic structure with static interfaces for impleme...
- Patent number 7,161,390
- Issue date Jan 9, 2007
- International Business Machines Corporation
- Anthony Gus Aipperspach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for reducing soft error rate in SRAM arrays us...
- Patent number 7,092,281
- Issue date Aug 15, 2006
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ON-CHIP DIAGNOSTIC CIRCUITRY MONITORING MULTIPLE CYCLES OF SIGNAL S...
- Publication number 20170242066
- Publication date Aug 24, 2017
- International Business Machines Corporation
- Anthony G. AIPPERSPACH
- G01 - MEASURING TESTING
Information Patent Application
DETECTING MAXIMUM VOLTAGE BETWEEN MULTIPLE POWER SUPPLIES FOR MEMOR...
- Publication number 20170047099
- Publication date Feb 16, 2017
- International Business Machines Corporation
- Anthony G. AIPPERSPACH
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTROSTATIC DISCHARGE PROTECTION DEVICE WITH POWER MANAGEMENT
- Publication number 20160322813
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Anthony G. Aipperspach
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
ELECTROSTATIC DISCHARGE PROTECTION DEVICE WITH POWER MANAGEMENT
- Publication number 20160322812
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Anthony G. Aipperspach
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
IMPLEMENTING ENHANCED PERFORMANCE DYNAMIC EVALUATION CIRCUIT BY COM...
- Publication number 20160180004
- Publication date Jun 23, 2016
- International Business Machines Corporation
- Anthony G. Aipperspach
- G01 - MEASURING TESTING
Information Patent Application
IMPLEMENTING ENHANCED PERFORMANCE DYNAMIC EVALUATION CIRCUIT BY COM...
- Publication number 20160180009
- Publication date Jun 23, 2016
- International Business Machines Corporation
- Anthony G. Aipperspach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVEL-SHIFTING LATCH
- Publication number 20160182052
- Publication date Jun 23, 2016
- International Business Machines Corporation
- Anthony G. Aipperspach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LEVEL-SHIFTING LATCH
- Publication number 20160182053
- Publication date Jun 23, 2016
- International Business Machines Corporation
- Anthony G. Aipperspach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE IMPEDANCE DRIVER FOR RESONANT CLOCK NETWORKS
- Publication number 20150002204
- Publication date Jan 1, 2015
- International Business Machines Corporation
- Anthony G. Aipperspach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
IMPLEMENTING INTEGRATED CIRCUIT MIXED DOUBLE DENSITY AND HIGH PERFO...
- Publication number 20130020712
- Publication date Jan 24, 2013
- International Business Machines Corporation
- Anthony G. Aipperspach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Implementing Precise Resistance Measurement for 2D Array Efuse Bit...
- Publication number 20100067319
- Publication date Mar 18, 2010
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Circuit for Implementing Efuse Resistance Screening
- Publication number 20090212850
- Publication date Aug 27, 2009
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Circuit for Implementing Enhanced Efuse Sense Circuit
- Publication number 20090201756
- Publication date Aug 13, 2009
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Circuit for Implementing Efuse Sense Amplifier Verification
- Publication number 20090201074
- Publication date Aug 13, 2009
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS FOR IMPLEMENTING EFUSE SENSE AMPLIFIER TESTING WITHOUT BL...
- Publication number 20090175106
- Publication date Jul 9, 2009
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Application
Techniques for Selecting a Voltage Source From Multiple Voltage Sou...
- Publication number 20090102289
- Publication date Apr 23, 2009
- Anthony G. Aipperspach
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
Staggered LBIST Clock Sequence for Noise (di/dt) Amelioration
- Publication number 20090063921
- Publication date Mar 5, 2009
- Anthony Gus Aipperspach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays
- Publication number 20080212396
- Publication date Sep 4, 2008
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Implementing Efuse Sense Amplifier Testing...
- Publication number 20080170449
- Publication date Jul 17, 2008
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Implementing Efuse Sense Amplifier Testing...
- Publication number 20080169843
- Publication date Jul 17, 2008
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G01 - MEASURING TESTING
Information Patent Application
Electrically Programmable Fuse Sense Circuit
- Publication number 20080157851
- Publication date Jul 3, 2008
- International Business Machines Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Application
Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays
- Publication number 20080117709
- Publication date May 22, 2008
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
DELAY MECHANISM FOR UNBALANCED READ/WRITE PATHS IN DOMINO SRAM ARRAYS
- Publication number 20080117695
- Publication date May 22, 2008
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Electrically Programmable Fuse Sense Circuit
- Publication number 20080106323
- Publication date May 8, 2008
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE
Information Patent Application
Asymmetrical Random Access Memory Cell, A Memory Comprising Asymmet...
- Publication number 20070165447
- Publication date Jul 19, 2007
- Otto Wagner
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and methods for predicting and/or calibrating memory yields
- Publication number 20070044049
- Publication date Feb 22, 2007
- International Business Machines Corporation
- Chad A. Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for accessing memory
- Publication number 20070019461
- Publication date Jan 25, 2007
- International Business Machines Corporation
- Chad Allen Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Glitch protect valid cell and method for maintaining a desired stat...
- Publication number 20070019454
- Publication date Jan 25, 2007
- International Business Machines (IBM) Corporation
- Derick G. Behrends
- G11 - INFORMATION STORAGE
Information Patent Application
Methods and apparatus for accessing memory
- Publication number 20060250842
- Publication date Nov 9, 2006
- International Business Machines Corporation
- Chad A. Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for reducing time delay through static bitline...
- Publication number 20060245240
- Publication date Nov 2, 2006
- IBM Corporation
- Anthony Gus Aipperspach
- G11 - INFORMATION STORAGE

Anthony G. Aipperspach

Person

Patents Grantslast 30 patents

On-chip diagnostic circuitry monitoring multiple cycles of signal s...

Detecting maximum voltage between multiple power supplies for memor...

Level-shifting latch

Electrostatic discharge protection device with power management

Level-shifting latch

Electrostatic discharge protection device with power management

Implementing enhanced performance dynamic evaluation circuit by com...

Implementing enhanced performance dynamic evaluation circuit by com...

Implementing low power, single master-slave elastic buffer

Implementing integrated circuit mixed double density and high perfo...

Implementing precise resistance measurement for 2D array efuse bit...

Apparatus for implementing eFuse sense amplifier testing without bl...

Method and circuit for implementing enhanced eFuse sense circuit

Method and circuit for implementing eFuse sense amplifier verification

Implementing Efuse sense amplifier testing without blowing the Efuse

Methods and apparatus for testing a memory

Asymmetrical random access memory cell, and a memory comprising asy...

Electrically programmable fuse sense circuit

Electrically programmable fuse sense circuit

Apparatus and methods for predicting and/or calibrating memory yields

Method for implementing eFuse sense amplifier testing without blowi...

Delay mechanism for unbalanced read/write paths in domino SRAM arrays

Pulse-width limited chip clock design

Methods and apparatus for accessing memory

Simplified method for limiting clock pulse width

Methods and apparatus for accessing memory

Glitch protect valid cell and method for maintaining a desired stat...

Array redundancy supporting multiple independent repairs

Dynamic latching logic structure with static interfaces for impleme...

Method and apparatus for reducing soft error rate in SRAM arrays us...

Patents Applicationslast 30 patents

ON-CHIP DIAGNOSTIC CIRCUITRY MONITORING MULTIPLE CYCLES OF SIGNAL S...

DETECTING MAXIMUM VOLTAGE BETWEEN MULTIPLE POWER SUPPLIES FOR MEMOR...

ELECTROSTATIC DISCHARGE PROTECTION DEVICE WITH POWER MANAGEMENT

ELECTROSTATIC DISCHARGE PROTECTION DEVICE WITH POWER MANAGEMENT

IMPLEMENTING ENHANCED PERFORMANCE DYNAMIC EVALUATION CIRCUIT BY COM...

IMPLEMENTING ENHANCED PERFORMANCE DYNAMIC EVALUATION CIRCUIT BY COM...

LEVEL-SHIFTING LATCH

LEVEL-SHIFTING LATCH

VARIABLE IMPEDANCE DRIVER FOR RESONANT CLOCK NETWORKS

IMPLEMENTING INTEGRATED CIRCUIT MIXED DOUBLE DENSITY AND HIGH PERFO...

Implementing Precise Resistance Measurement for 2D Array Efuse Bit...

Method and Circuit for Implementing Efuse Resistance Screening

Method and Circuit for Implementing Enhanced Efuse Sense Circuit

Method and Circuit for Implementing Efuse Sense Amplifier Verification

APPARATUS FOR IMPLEMENTING EFUSE SENSE AMPLIFIER TESTING WITHOUT BL...

Techniques for Selecting a Voltage Source From Multiple Voltage Sou...

Staggered LBIST Clock Sequence for Noise (di/dt) Amelioration

Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays

Method and Apparatus for Implementing Efuse Sense Amplifier Testing...

Method and Apparatus for Implementing Efuse Sense Amplifier Testing...

Electrically Programmable Fuse Sense Circuit

Delay Mechanism for Unbalanced Read/Write Paths in Domino SRAM Arrays

DELAY MECHANISM FOR UNBALANCED READ/WRITE PATHS IN DOMINO SRAM ARRAYS

Electrically Programmable Fuse Sense Circuit

Asymmetrical Random Access Memory Cell, A Memory Comprising Asymmet...

Apparatus and methods for predicting and/or calibrating memory yields

Methods and apparatus for accessing memory

Glitch protect valid cell and method for maintaining a desired stat...

Methods and apparatus for accessing memory

Method and apparatus for reducing time delay through static bitline...