Antonio Luis Pacheco Rotondaro

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device having a dislocation loop located within a bou...
- Patent number 7,691,714
- Issue date Apr 6, 2010
- Texas Instruments Incorporated
- Antonio Luis Pacheco Rotondaro
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Work function control of metals
- Patent number 7,601,577
- Issue date Oct 13, 2009
- Texas Instruments Incorporated
- James Joseph Chambers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Defect control in gate dielectrics
- Patent number 7,601,578
- Issue date Oct 13, 2009
- Texas Instruments Incorporated
- Luigi Colombo
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Crystallographic preferential etch to define a recessed-region for...
- Patent number 7,528,072
- Issue date May 5, 2009
- Texas Instruments Incorporated
- Antonio Luis Pacheco Rotondaro
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods to selectively protect NMOS regions, PMOS regions, and gate...
- Patent number 7,514,309
- Issue date Apr 7, 2009
- Texas Instruments Incorporated
- Seetharaman Sridhar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having multiple work functions and method of m...
- Patent number 7,226,826
- Issue date Jun 5, 2007
- Texas Instruments Incorporated
- Husam N. Alshareef
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to reduce transistor gate to source/drain overlap capacitanc...
- Patent number 7,199,011
- Issue date Apr 3, 2007
- Texas Instruments Incorporated
- Majid Movahed Mansoori
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to selectively strain NMOS devices using a cap poly layer
- Patent number 7,172,936
- Issue date Feb 6, 2007
- Texas Instruments Incorporated
- Seetharaman Sridhar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for extraction of C-V characteristics of ultra-th...
- Patent number 7,088,123
- Issue date Aug 8, 2006
- Texas Instruments Incorporated
- Jau-Yuann Yang
- G01 - MEASURING TESTING
Information Patent Grant
Control of high-k gate dielectric film composition profile for prop...
- Patent number 7,071,519
- Issue date Jul 4, 2006
- Texas Instruments Incorporated
- Luigi Colombo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of indium to define work function of p-type doped polysilicon
- Patent number 7,026,218
- Issue date Apr 11, 2006
- Texas Instruments Incorporated
- Antonio Luis Pacheco Rotondaro
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE WITH GATE-UNDERCUTTING RECESSED REGION
- Publication number 20110318901
- Publication date Dec 29, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Antonio Luis Pacheco ROTONDARO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
N-TYPE SEMICONDUCTOR COMPONENT WITH IMPROVED DOPANT IMPLANTATION PR...
- Publication number 20080268628
- Publication date Oct 30, 2008
- Puneet Kohli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to prevent defects on SRAM cells that incorporate selective...
- Publication number 20070290192
- Publication date Dec 20, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Antonio Luis Pacheco Rotondaro
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Work function control of metals
- Publication number 20070054446
- Publication date Mar 8, 2007
- TEXAS INSTRUMENTS INCORPORATED
- James Joseph Chambers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods to selectively protect NMOS regions, PMOS regions, and gate...
- Publication number 20070020839
- Publication date Jan 25, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Seetharaman Sridhar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Control of high -k gate dielectric film composition profile for pro...
- Publication number 20040129969
- Publication date Jul 8, 2004
- Luigi Colombo
- H01 - BASIC ELECTRIC ELEMENTS

Antonio Luis Pacheco Rotondaro

Person

Patents Grantslast 30 patents

Semiconductor device having a dislocation loop located within a bou...

Work function control of metals

Defect control in gate dielectrics

Crystallographic preferential etch to define a recessed-region for...

Methods to selectively protect NMOS regions, PMOS regions, and gate...

Semiconductor device having multiple work functions and method of m...

Method to reduce transistor gate to source/drain overlap capacitanc...

Method to selectively strain NMOS devices using a cap poly layer

System and method for extraction of C-V characteristics of ultra-th...

Control of high-k gate dielectric film composition profile for prop...

Use of indium to define work function of p-type doped polysilicon

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE WITH GATE-UNDERCUTTING RECESSED REGION

N-TYPE SEMICONDUCTOR COMPONENT WITH IMPROVED DOPANT IMPLANTATION PR...

Method to prevent defects on SRAM cells that incorporate selective...

Work function control of metals

Methods to selectively protect NMOS regions, PMOS regions, and gate...

Control of high -k gate dielectric film composition profile for pro...