Anubhav Khandelwal

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Control gate signal for data retention in nonvolatile memory
- Patent number 12,087,363
- Issue date Sep 10, 2024
- SanDisk Technologies LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Grant
Control gate signal for data retention in nonvolatile memory
- Patent number 11,605,430
- Issue date Mar 14, 2023
- SanDisk Technologies LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Grant
System and methods for programming nonvolatile memory having partia...
- Patent number 11,581,049
- Issue date Feb 14, 2023
- SanDisk Technologies LLC
- Kazuki Isozumi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory apparatus and method of operation using periodic normal eras...
- Patent number 11,574,693
- Issue date Feb 7, 2023
- SanDisk Technologies LLC
- Chin-Yi Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming techniques for memory devices having partial drain-side...
- Patent number 11,562,798
- Issue date Jan 24, 2023
- SanDisk Technologies LLC
- Parth Amin
- G11 - INFORMATION STORAGE
Information Patent Grant
“Read after erase” method for catching single word line “slow to er...
- Patent number 11,545,225
- Issue date Jan 3, 2023
- SanDisk Technologies LLC
- Parth Amin
- G11 - INFORMATION STORAGE
Information Patent Grant
Application based verify level offsets for non-volatile memory
- Patent number 11,482,289
- Issue date Oct 25, 2022
- SanDisk Technologies LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory programming with selectively skipped bitscans and fewer veri...
- Patent number 11,468,950
- Issue date Oct 11, 2022
- SanDisk Technologies LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Grant
Countermeasures for periodic over programming for non-volatile memory
- Patent number 11,450,393
- Issue date Sep 20, 2022
- SanDisk Technologies LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming techniques with fewer verify pulses to improve performance
- Patent number 11,410,739
- Issue date Aug 9, 2022
- SanDisk Technologies LLC
- Abhijith Prakash
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing post-read disturb in a nonvolatile memory device
- Patent number 11,139,030
- Issue date Oct 5, 2021
- SanDisk Technologies LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for high-performance write operations
- Patent number 10,878,926
- Issue date Dec 29, 2020
- SanDisk Technologies LLC
- Pitamber Shukla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System handling for first read read disturb
- Patent number 10,790,031
- Issue date Sep 29, 2020
- Western Digital Technologies, Inc.
- Piyush Sagdeo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing post-read disturb in a nonvolatile memory device
- Patent number 10,726,891
- Issue date Jul 28, 2020
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read verify for improved soft bit information for non-volatile memo...
- Patent number 10,636,504
- Issue date Apr 28, 2020
- SanDisk Technologies LLC
- Philip David Reusswig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boundary word line voltage shift
- Patent number 10,559,366
- Issue date Feb 11, 2020
- Western Digital Technologies, Inc.
- Zhenlei Shen
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for string-based erase verify to create partial g...
- Patent number 10,535,411
- Issue date Jan 14, 2020
- Western Digital Technologies, Inc.
- Mohan Dunga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive erase fail bit criteria
- Patent number 10,482,986
- Issue date Nov 19, 2019
- Western Digital Technologies, Inc.
- Chao-Han Cheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for high-performance write operations
- Patent number 10,460,816
- Issue date Oct 29, 2019
- SanDisk Technologies LLC
- Pitamber Shukla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory with methods to reduce creep-up field between d...
- Patent number 10,204,689
- Issue date Feb 12, 2019
- SanDisk Technologies LLC
- Ching-Huang Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for reducing read disturb in partially written blocks of...
- Patent number 9,978,456
- Issue date May 22, 2018
- SanDisk Technologies LLC
- Anubhav Khandelwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems that selectively inhibit and enable programming...
- Patent number 9,620,238
- Issue date Apr 11, 2017
- SanDisk Technologies LLC
- Anubhav Khandelwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced dynamic read process with single-level cell segmentation
- Patent number 9,195,587
- Issue date Nov 24, 2015
- SanDisk Technologies Inc.
- Mrinal Kochar
- G11 - INFORMATION STORAGE
Information Patent Grant
Ramping pass voltage to enhance channel boost in memory device
- Patent number 8,644,075
- Issue date Feb 4, 2014
- SanDisk Technologies Inc.
- Gerrit Jan Hemink
- G11 - INFORMATION STORAGE
Information Patent Grant
Ramping pass voltage to enhance channel boost in memory device, wit...
- Patent number 8,526,233
- Issue date Sep 3, 2013
- SanDisk Technologies Inc.
- Gerrit Jan Hemink
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing neighbor read disturb
- Patent number 8,472,266
- Issue date Jun 25, 2013
- SanDisk Technologies Inc.
- Anubhav Khandelwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase and programming techniques to reduce the widening of state di...
- Patent number 8,416,624
- Issue date Apr 9, 2013
- SanDisk Technologies, Inc
- Bo Lei
- G11 - INFORMATION STORAGE
Information Patent Grant
Two pass erase for non-volatile storage
- Patent number 8,264,890
- Issue date Sep 11, 2012
- SanDisk Technologies Inc.
- Nima Mokhlesi
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming memory with bit line floating to reduce channel-to-floa...
- Patent number 8,089,815
- Issue date Jan 3, 2012
- SanDisk Technologies Inc.
- Yan Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Two pass erase for non-volatile storage
- Patent number 7,907,449
- Issue date Mar 15, 2011
- SanDisk Corporation
- Dana Lee
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY
- Publication number 20240395328
- Publication date Nov 28, 2024
- SANDISK TECHNOLOGIES LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY WITH FASTER POST-ERASE DEFECT TESTING
- Publication number 20240290412
- Publication date Aug 29, 2024
- SANDISK TECHNOLOGIES LLC
- Sai Gautham Thoppa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERA DETECTION METHOD TO CATCH ERASE FAIL
- Publication number 20240161858
- Publication date May 16, 2024
- SANDISK TECHNOLOGIES LLC
- Parth Amin
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAM PULSE DURATION INCREASE FOR NAND PROGRAM FAILURE
- Publication number 20240127891
- Publication date Apr 18, 2024
- SANDISK TECHNOLOGIES LLC
- Abu Naser Zainuddin
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY
- Publication number 20230186993
- Publication date Jun 15, 2023
- SANDISK TECHNOLOGIES LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
?READ AFTER ERASE? METHOD FOR CATCHING SINGLE WORD LINE ?SLOW TO E...
- Publication number 20220415413
- Publication date Dec 29, 2022
- SANDISK TECHNOLOGIES LLC
- Parth Amin
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY APPARATUS AND METHOD OF OPERATION USING PERIODIC NORMAL ERAS...
- Publication number 20220399066
- Publication date Dec 15, 2022
- SANDISK TECHNOLOGIES LLC
- Chin-Yi Chen
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING TECHNIQUES FOR MEMORY DEVICES HAVING PARTIAL DRAIN-SIDE...
- Publication number 20220399063
- Publication date Dec 15, 2022
- SanDisk Technologies LLC
- Parth Amin
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY APPARATUS AND METHOD OF OPERATION USING DYNAMIC MAX PROGRAM...
- Publication number 20220399058
- Publication date Dec 15, 2022
- SANDISK TECHNOLOGIES LLC
- Parth Amin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHODS FOR PROGRAMMING NONVOLATILE MEMORY HAVING PARTIA...
- Publication number 20220383967
- Publication date Dec 1, 2022
- SANDISK TECHNOLOGIES LLC
- Kazuki Isozumi
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY PROGRAMMING WITH SELECTIVELY SKIPPED BITSCANS AND FEWER VERI...
- Publication number 20220336019
- Publication date Oct 20, 2022
- SANDISK TECHNOLOGIES LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
COUNTERMEASURES FOR PERIODIC OVER PROGRAMMING FOR NON-VOLATILE MEMORY
- Publication number 20220293197
- Publication date Sep 15, 2022
- SANDISK TECHNOLOGIES LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
APPLICATION BASED VERIFY LEVEL OFFSETS FOR NON-VOLATILE MEMORY
- Publication number 20220284971
- Publication date Sep 8, 2022
- SANDISK TECHNOLOGIES LLC
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY
- Publication number 20220284961
- Publication date Sep 8, 2022
- SANDISK TECHNOLOGIES LLC
- Abhijith Prakash
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING POST-READ DISTURB IN A NONVOLATILE MEMORY DEVICE
- Publication number 20200258558
- Publication date Aug 13, 2020
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS
- Publication number 20200035313
- Publication date Jan 30, 2020
- SanDisk Technologies LLC
- Pitamber Shukla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY WORD LINE VOLTAGE SHIFT
- Publication number 20190304550
- Publication date Oct 3, 2019
- Western Digital Technologies, Inc.
- ZHENLEI SHEN
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS
- Publication number 20190180831
- Publication date Jun 13, 2019
- SanDisk Technologies LLC
- Pitamber Shukla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ VERIFY FOR IMPROVED SOFT BIT INFORMATION FOR NON-VOLATILE MEMO...
- Publication number 20190130982
- Publication date May 2, 2019
- SanDisk Technologies LLC
- Philip David Reusswig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE ERASE FAIL BIT CRITERIA
- Publication number 20190122741
- Publication date Apr 25, 2019
- Western Digital Technologies, Inc.
- Chao-Han Cheng
- G11 - INFORMATION STORAGE
Information Patent Application
Non-volatile Memory With Methods To Reduce Creep-Up Field Between D...
- Publication number 20190035480
- Publication date Jan 31, 2019
- SanDisk Technologies LLC
- Ching-Huang Lu
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR STRING-BASED ERASE VERIFY TO CREATE PARTIAL G...
- Publication number 20180342304
- Publication date Nov 29, 2018
- Western Digital Technologies, Inc.
- Mohan Dunga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Reducing Read Disturb in Partially Written Blocks of...
- Publication number 20160141046
- Publication date May 19, 2016
- SanDisk Technologies, Inc.
- Anubhav Khandelwal
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING AND VERIFYING FOR NON-VOLATILE STORAGE
- Publication number 20150206593
- Publication date Jul 23, 2015
- SANDISK TECHNOLOGIES INC.
- Anubhav Khandelwal
- G11 - INFORMATION STORAGE
Information Patent Application
Enhanced Dynamic Read Process with Single-Level Cell Segmentation
- Publication number 20140258590
- Publication date Sep 11, 2014
- Mrinal Kochar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ramping Pass Voltage To Enhance Channel Boost In Memory Device
- Publication number 20130314987
- Publication date Nov 28, 2013
- SANDISK TECHNOLOGIES INC.
- Gerrit Jan Hemink
- G11 - INFORMATION STORAGE
Information Patent Application
Ramping Pass Voltage To Enhance Channel Boost In Memory Device, Wit...
- Publication number 20120300550
- Publication date Nov 29, 2012
- Gerrit Jan Hemink
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING NEIGHBOR READ DISTURB
- Publication number 20120250414
- Publication date Oct 4, 2012
- Anubhav Khandelwal
- G11 - INFORMATION STORAGE
Information Patent Application
Erase and Programming Techniques to Reduce the Widening of State Di...
- Publication number 20110286279
- Publication date Nov 24, 2011
- Bo Lei
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING MEMORY WITH BIT LINE FLOATING TO REDUCE CHANNEL-TO-FLOA...
- Publication number 20110122695
- Publication date May 26, 2011
- Yan Li
- G11 - INFORMATION STORAGE

Anubhav Khandelwal

Person

Patents Grantslast 30 patents

Control gate signal for data retention in nonvolatile memory

Control gate signal for data retention in nonvolatile memory

System and methods for programming nonvolatile memory having partia...

Memory apparatus and method of operation using periodic normal eras...

Programming techniques for memory devices having partial drain-side...

“Read after erase” method for catching single word line “slow to er...

Application based verify level offsets for non-volatile memory

Memory programming with selectively skipped bitscans and fewer veri...

Countermeasures for periodic over programming for non-volatile memory

Programming techniques with fewer verify pulses to improve performance

Reducing post-read disturb in a nonvolatile memory device

Systems and methods for high-performance write operations

System handling for first read read disturb

Reducing post-read disturb in a nonvolatile memory device

Read verify for improved soft bit information for non-volatile memo...

Boundary word line voltage shift

System and method for string-based erase verify to create partial g...

Adaptive erase fail bit criteria

Systems and methods for high-performance write operations

Non-volatile memory with methods to reduce creep-up field between d...

Techniques for reducing read disturb in partially written blocks of...

Methods and systems that selectively inhibit and enable programming...

Enhanced dynamic read process with single-level cell segmentation

Ramping pass voltage to enhance channel boost in memory device

Ramping pass voltage to enhance channel boost in memory device, wit...

Reducing neighbor read disturb

Erase and programming techniques to reduce the widening of state di...

Two pass erase for non-volatile storage

Programming memory with bit line floating to reduce channel-to-floa...

Two pass erase for non-volatile storage

Patents Applicationslast 30 patents

CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY

NON-VOLATILE MEMORY WITH FASTER POST-ERASE DEFECT TESTING

VERA DETECTION METHOD TO CATCH ERASE FAIL

PROGRAM PULSE DURATION INCREASE FOR NAND PROGRAM FAILURE

CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY

?READ AFTER ERASE? METHOD FOR CATCHING SINGLE WORD LINE ?SLOW TO E...

MEMORY APPARATUS AND METHOD OF OPERATION USING PERIODIC NORMAL ERAS...

PROGRAMMING TECHNIQUES FOR MEMORY DEVICES HAVING PARTIAL DRAIN-SIDE...

MEMORY APPARATUS AND METHOD OF OPERATION USING DYNAMIC MAX PROGRAM...

SYSTEM AND METHODS FOR PROGRAMMING NONVOLATILE MEMORY HAVING PARTIA...

MEMORY PROGRAMMING WITH SELECTIVELY SKIPPED BITSCANS AND FEWER VERI...

COUNTERMEASURES FOR PERIODIC OVER PROGRAMMING FOR NON-VOLATILE MEMORY

APPLICATION BASED VERIFY LEVEL OFFSETS FOR NON-VOLATILE MEMORY

CONTROL GATE SIGNAL FOR DATA RETENTION IN NONVOLATILE MEMORY

REDUCING POST-READ DISTURB IN A NONVOLATILE MEMORY DEVICE

SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS

BOUNDARY WORD LINE VOLTAGE SHIFT

SYSTEMS AND METHODS FOR HIGH-PERFORMANCE WRITE OPERATIONS

READ VERIFY FOR IMPROVED SOFT BIT INFORMATION FOR NON-VOLATILE MEMO...

ADAPTIVE ERASE FAIL BIT CRITERIA

Non-volatile Memory With Methods To Reduce Creep-Up Field Between D...

SYSTEM AND METHOD FOR STRING-BASED ERASE VERIFY TO CREATE PARTIAL G...

Techniques for Reducing Read Disturb in Partially Written Blocks of...

PROGRAMMING AND VERIFYING FOR NON-VOLATILE STORAGE

Enhanced Dynamic Read Process with Single-Level Cell Segmentation

Ramping Pass Voltage To Enhance Channel Boost In Memory Device

Ramping Pass Voltage To Enhance Channel Boost In Memory Device, Wit...

REDUCING NEIGHBOR READ DISTURB

Erase and Programming Techniques to Reduce the Widening of State Di...

PROGRAMMING MEMORY WITH BIT LINE FLOATING TO REDUCE CHANNEL-TO-FLOA...