Arno Zechmann

Person

Villach, AT

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor wafer dicing crack prevention using chip peripheral t...
- Patent number 10,903,120
- Issue date Jan 26, 2021
- Infineon Technologies Austria AG
- Arno Zechmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor wafer dicing crack prevention using chip peripheral t...
- Patent number 10,256,149
- Issue date Apr 9, 2019
- Infineon Technologies Austria AG
- Arno Zechmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor wafer and method
- Patent number 9,660,037
- Issue date May 23, 2017
- Infineon Technologies Austria AG
- Arno Zechmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of electrodepositing gold on a copper seed layer to form a g...
- Patent number 9,425,090
- Issue date Aug 23, 2016
- Infineon Technologies Austria AG
- Arno Zechmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit including power transistor cells and a connectin...
- Patent number 8,502,274
- Issue date Aug 6, 2013
- Infineon Technologies AG
- Kurt Matoy
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
WAFER BASED BEOL PROCESS FOR CHIP EMBEDDING
- Publication number 20190259874
- Publication date Aug 22, 2019
- INFINEON TECHNOLOGIES AG
- Paul Ganitzer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Wafer Dicing Crack Prevention Using Chip Peripheral T...
- Publication number 20190043757
- Publication date Feb 7, 2019
- Infineon Technologies Austria AG
- Arno Zechmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Wafer Dicing Crack Prevention Using Chip Peripheral T...
- Publication number 20180247869
- Publication date Aug 30, 2018
- Infineon Technologies Austria AG
- Arno Zechmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR WAFER AND METHOD
- Publication number 20170170282
- Publication date Jun 15, 2017
- Infineon Technologies Austria AG
- Arno Zechmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device Having Gold Metallization Structures
- Publication number 20160336272
- Publication date Nov 17, 2016
- Infineon Technologies Austria AG
- Arno Zechmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF ELECTRODEPOSITING GOLD ON A COPPER SEED LAYER TO FORM A G...
- Publication number 20160086847
- Publication date Mar 24, 2016
- Arno Zechmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER BASED BEOL PROCESS FOR CHIP EMBEDDING
- Publication number 20150221764
- Publication date Aug 6, 2015
- INFINEON TECHNOLOGIES AG
- Paul Ganitzer
- H01 - BASIC ELECTRIC ELEMENTS

Arno Zechmann

Person

Patents Grantslast 30 patents

Semiconductor wafer dicing crack prevention using chip peripheral t...

Semiconductor wafer dicing crack prevention using chip peripheral t...

Semiconductor wafer and method

Method of electrodepositing gold on a copper seed layer to form a g...

Integrated circuit including power transistor cells and a connectin...

Patents Applicationslast 30 patents

WAFER BASED BEOL PROCESS FOR CHIP EMBEDDING

Semiconductor Wafer Dicing Crack Prevention Using Chip Peripheral T...

Semiconductor Wafer Dicing Crack Prevention Using Chip Peripheral T...

SEMICONDUCTOR WAFER AND METHOD

Semiconductor Device Having Gold Metallization Structures

METHOD OF ELECTRODEPOSITING GOLD ON A COPPER SEED LAYER TO FORM A G...

WAFER BASED BEOL PROCESS FOR CHIP EMBEDDING