Various embodiments relate to a wafer based BEOL (back end of line) process for chip embedding.
Packaging is the final stage of semiconductor device fabrication, in which the small block of processed semiconductor, i.e. the chip, is placed in a supporting case that prevents physical damage and corrosion. The case, which is commonly referred to as “package”, supports the electrical contacts which connect the chip to a circuit board.
A standard packaging process is usually based on bonding and molding. Interconnects are realized by a galvanic processes and the die is protected with a laminate.
In a new packaging concept, also referred to as Blade package, a chip is attached onto a circuit board. Both the front side and the back side of the chip are electrically contacted with the leadframe via a metal layer. The Blade package is a vertical transistor package optimized for high current handling and easy circuit board layout. Using this technology makes it possible to realize products with lowest on state resistances and highest power density without compromises in performance and cooling.
However, it has been found that common chip concepts, for example relying on SFETx (x standing for 3, 4 or 5) technology, also referred to as “double poly” (i.e. designs with two electrodes insulated from one another in a trench) or its brand name Optimos, are not suitable for the Blade package due to the nature of the metallisation and/or passivation process and therefore, a solution to that problem would be desirable.
In various embodiments a semiconductor device is provided, including a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; and a contact structure provided over the drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer.
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.
The word “exemplary” is used herein to mean “serving as an example, instance, or illustration”. Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.
The Blade package may be understood as an application of the printed circuit board (PCB) in the semiconductor manufacturing technology. In the packaging process, a die may be attached to a leadframe by soldering, such that the back side of the die may be electrically contactable. The front side of the die may be also electrically contacted by a metal layer.
The transistor 100 includes a semiconductor body 102 which includes a semiconducting material 103, for example a layer of the semiconductor material 103, and a back side metal layer 104. The back side metal layer 104 is provided on the bottom surface of the layer of semiconductor material 103 and may be used as a thermally optimized die attach by means of diffusion soldering or eutectic bonding. The semiconductor material 103 may be a part of a die incorporating a functional circuit. Differently doped wells may be created within the layer of semiconductor material 103 by means of doping. In this case, a gate electrode 106 is provided in the layer of semiconductor material 103. A first drift region 108 and a second drift region 110 are provided in the layer of semiconductor material 103 adjacent to the gate electrode 106. A layer of dielectric material isolating the gate electrode 106 from the surrounding semiconductor material 103, e.g. from the drift regions 108, 110, is not shown in
Over the upper surface of the semiconductor body 102 a gate portion 112 is provided which may be electrically coupled to the gate electrode 106. The gate portion 112 is covered by a layer of dielectric material 122, a so-called inter layer dielectric (ILD). The dielectric material may include silicon oxide or silicon nitride. A first metal layer 118 is disposed over the upper surface of the semiconductor body 102 on both sides of the gate portion 112. The first metal layer 118 is subdivided in two or in general more portions thereof, for example a left portion and a right portion referring to the relative locations of the respective portions of the first metal layer 118 on the semiconductor body 102, which are separated from one another by the gate portion 112 and are further isolated from the gate portion 112 by the dielectric material 122. A further gate portion 114 is provided on the upper surface of the semiconductor body 102 adjacent to the left portion of the first metal layer 118 and isolated therefrom by the dielectric material 122 which covers or surrounds the further gate portion 114 in the same way as the gate portion 112 is surrounded by the dielectric material 122. A further first metal layer 118* is provided on the upper surface of the semiconductor body 102 adjacent to the right portion of the first metal layer 118. The further first metal layer 118* is separated from the right portion of the first metal layer 118 by a block of dielectric material 122.
A second metal layer 124, 124* is provided on top of every first metal layer 118, 118*. The second metal layer 124, 124* may include copper. The left portion of the second metal layer 124 over the left and right portion of the first metal layer 118 is a continuous second metal layer 124, i.e. the left portion and the right portion of the first metal layer 118 are electrically coupled to one another by means of the second metal layer 124. The other, right portion of the second metal layer 124* on top of the further first metal layer 118* is electrically isolated from the continuous second metal layer 124 by means of a passivation material 126 provided in a gap separating the left portion of the second metal layer 124 form the right portion of the second metal layer 124*. The passivation material is further provided over the leftmost layer of dielectric material 122 and also on the right side of the right portion of the second metal layer 124*. Due to the nature of the manufacturing process of the field effect transistor 100 involving heating, an intermetallic phase 120, 120* is present at every interface between the first metal layer 118, 118* and the second metal layer 124, 124*.
The left portion and the right portion of the first metal layer 118 and the further portion of the first metal layer 118* may be formed in the same manufacturing process. In fact, a continuous first metal layer, for example including aluminium, may be provided over the top surface of the semiconductor body 102 and subsequently the continuous first metal layer may be structured appropriately (e.g. by an appropriate masking process followed by an etching process) to yield the pattern of first metal portions shown in
Returning back to the cross-sectional view presented in
In the scope of this specification, the reference numbers of layers falling into the scope of the gate contact carry a suffix in the form of asterisk (*), whereas corresponding layers falling into the scope of the source contacts carry the same reference numbers without the asterisk.
The thickness of the layer including the semiconductor material 103 in standard manufacturing processes is approximately in the range of approximately 40 μm to approximately 60 μm. The layers provided on the surface of the semiconductor body 102 add at least approximately further 20 μm, such that the thickness of the whole structure of the vertical field effect transistor 100 shown in
The design of the vertical field effect transistor 100 shown in
One undesirable aspect of the vertical transistor 100 design is the formation of the intermetallic phase 120, 120* at the interfaces between the several portions of the first metal layer 118, 118* and the portions of the second metal layer 124, 124*. The formation of the intermetallic phase 120, 120* is caused by high temperature process steps during the manufacture of the vertical field effect transistor 100. The intermetallic phase 120, 120* is unwanted in the Blade assembly process and is seen as a flawed region since it is mechanically unstable and thus prone to cause delamination within the device. It is further susceptible to increased etching with respect to other materials such that is reduce the process reliability during the assembly of the device.
A second problematic aspect to be mentioned relates to the second metallic layer 124, 124*. Since structuring of copper layers is rather difficult, the standard thickness of the second metal layer 124, 124* leads to an insufficient thickness after roughening of the copper layer. During provision of vias through a uniform layer of the passivation material 126 by means of a laser, for example, that thin layer may suffer from melting open, down to materials located beneath, for example down to the intermetallic phase 120, 120* or even down to the level of the first metal layer 118, 118* which then becomes exposed, rendering the electrical behaviour of the corresponding electrical contact less or oven predictable.
Furthermore, as shown in
Last but not least, the conventional passivation procedure may prove problematic, as the openings in the passivation material 126 exposing the second metal layer 124, 124*, as mentioned above, may lead to the already too thin second metal layer 124, 124* (usually copper) to be exposed to the roughing procedure performed on the device during its manufacture.
In view of the above problems, the design of the vertical field effect transistor 100 shown in
The semiconductor device 200 includes the semiconductor body 103 having the semiconductor material 103 (e.g. a layer 103 of semiconductor material) and the back side metal layer 104 provided on the bottom side of the semiconductor material 103. The doped structures within the semiconductor material 103 may correspond to the ones described with respect to
The semiconductor device 200 according to various embodiments shown in
The first contact structure 204 may correspond to a first source contact, the second contact structure 206 may correspond to a second source contact and the third contact structure 208 may correspond to a gate contact structure. The reference numbers of layers belonging to the gate contact structure are additionally marked with an asterisk, even though structurally they may be similar or substantially equal to the other contact structures. As the contact structures may be structurally similar, only the first contact structure 204 will be described in detail. Even though the contact structures may be substantially similar, they may differ in their dimensions or specific materials used such that different materials may be used for a given layer as long as they satisfy certain requirements such as conductivity or availability of etching agents, just to name two examples.
The first contact structure may include the first metal layer 118, an adhesion layer 202 arranged over the first metal layer 118 and a second metal layer 124 arranged over the adhesion layer 202. The first metal 118 layer may include aluminium (Al) or an aluminium copper alloy, wherein the content of copper may ammount to approximately 0.5%. The andesion layer 202 may include titatnium (Ti), tantalum (Ta), titatnium tungsten (TiW) or other refractive metals. The second metal layer 124 may include copper (Cu).
As already mentioned, the contact structures 204, 206, 208 are electrically separated from one another by a layer of dielectric material 122 and portions of the passivation material 126 provided on the layers of dielectric material 122. Furthermore, the passivation material 126 may encapsulate the contact structures such that they are not exposed to the exterior. However, openings in the passivation material may be provided to expose the second metal layer 124, 124* for electrical contacting, of which one opening 128 is shown in
In the following, the differences between the field effect transistor design presented in
The adhesion layer 202, 202* provided between the first metal layer 118, 118* and the second metal layer 124, 124* may offer several effects. On the one hand, the adhesion layer 202, 202* may improve the adhesion between the first metal layer 118, 118* and the second metal layer 124, 124*. It has been observed that the mechanical stress within the Blade package is increased in comparison to other standard packages, for example the Sx08 package. The Sx08 package may refer to a standard SMD (surface-mounted device) leadless mold package with a leadframe to which a chip is soldered to. The Sx08 package may be further characterized by a wire bonded or clip soldered gate contact and an ordinary clip soldered source interconnect. Despite providing an optimal boundary surface between the first metal layer 118, 118* and the second metal layer 124, 124*, for example between Al and Cu, via the corresponding intermetallic phases with a thickness of approximately 700 nm, delamination still occurred in typical stress tests. By providing the adhesion layer 202, 202* including an Al and Cu separating material such as Ti, Ta or TiW, a better adhesion between the surface of the first metal layer 118, 118* and the surface of the second metal layer 124, 124* may be achieved and delamination at that interface may be avoided. On the other hand, the adhesion layer 202, 202* may increase the range of available manufacturing temperatures during manufacturing processes such as providing the passivation layer, laser-drilling of vias for metallic interconnects. For example, depositing an imide based passivation is hardly possible without formation of intermetallic phases if the adhesion layer 202, 202* is not in place. The temperature required for imide passivation curing leads to a very strong intermetallic phase formation which, in effect, renders the corresponding electrical contact inoperable. In that sense, the adhesion layer 202, 202* may be seen as a layer preventing a reaction between the first metal layer 118, 118* and the second metal layer 124, 124*, for example during the imide passivation curing and may therefore be a reaction preventing and adhesion layer 202. Furthermore, the adhesion layer 202, 202* may increase the process reliability, since it provides a solid stoppage layer during the process of providing openings 128 in the passivation material 126 by a laser. In other words, the adhesion layer 202, 202* may prevent a faulty drilling of the via hole (opening 128) beyond the adhesion layer 202, 202*. With regard to this aspect, the non-existence of the intermetallic phase 120, 120* (see
The thickness of the second metal layer 124, 124* is increased with respect to standard designs and may lie in the region of 5 μm or more and may amount to 6 μm, 7 μm, 9 μm, 10 μm or more, for example. The increased thickness of the second metal layer 124, 124* allows for a secure roughening thereof which takes place at a later time during the manufacturing process. A thickness of the second metal layer 124, 124* below 5 μm may be critical in that respect as during the roughening process it may be completely removed at some spots. The provision of a thicker second metal layer 124, 124* may further increase the thermal capacity and the stability with regard to electromigration. Those aspects become, determined by the system, particularly relevant at the circumferential edge of the interface between the opening 128 (or via) and the second metal layer 124, 124*. During operation, a steady current flow approximately 3.5 A may be carried by the via which may have a diameter of approximately 50 μm. However, the current density within the bulk of the material filling the via, e.g. copper, is practically zero as the current predominantly flows at the edge of the block of material filling the via, e.g. The transition from the via to the second metal layer 124, 124* may be particularly critical at the circumferential edge of the via in common designs having a thin layer of the second metal layer 124, 124* as the thin metal layer 124, 124* may need to handle very high current densities. Here, the provision of a thicker second metal layer 124, 124* in accordance with various embodiments may be beneficial. A thicker second metal layer 124, 124* translating into a higher conductivity, may enable a wider field of design possibilities and may remove the necessity to electrically connect each source contact at a dense contact spacing by a via to achieve a homogenous current distribution. Furthermore, the provision of a thicker second metal layer 124, 124* may increase the robustness of the corresponding field effect transistor in avalanche mode. In case of copper as the material comprised by the second metal layer 124, 124*, common deposition procedures such as PVD (physical vapour deposition) or ECD (electrochemical deposition) may be used.
As shown in
The semiconductor device 200 according to various embodiments may further include a tungsten layer (not shown in
The layer of passivation material 126 may include various organic materials such as imide or epoxy. After the passivation material 126 has been deposited on the semiconductor device 200 according to various embodiments, the openings 128 may be provided in the passivation material 126 for contacting the second metal layer 124, 124*, for example by a laser. However, the passivation layer 126 may remain unperforated or “unopened” (i.e. without openings 128 being provided therein) and the openings 128 may be provided therein, for example by drilling with a laser, when the wafer is being diced by means of a saw frame. This allows more flexibility with respect to the used package technology (such as die attach, roughening of the second metal layer) and may lead to a more stable mechanical connection between the chip and the package.
A further difference between the standard vertical field effect transistor 100 shown in
The electrical and thermal coupling of the semiconductor device 200 according to various embodiments to the leadframe may be achieved by a thin metallic soldering connection. The soldering connection as such may be performed by means of diffusion soldering or eutectic soldering. The materials used for that process may include metal compounds on the basis of gold (Au), tin (Sn) and/or copper (Cu).
The aspects described above are based on structural features which have been also explained on the basis of
In
In accordance with various embodiments, a semiconductor device is provided which may include a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; and a contact structure provided over the drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer.
According to various further embodiments, the semiconductor device may further include a further drift region arranged adjacent to the gate electrode such that the gate electrode may be arranged between the two drift regions.
According to various further embodiments the semiconductor device may further include a further contact structure provided over the further drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer.
According to various further embodiments of the semiconductor device the second contact structure may be laterally separated from the first contact structure.
According to various further embodiments of the semiconductor device the first metal layer of the contact structure and the first metal layer of the further contact structure may include aluminium.
According to various further embodiments of the semiconductor device the adhesion layer of the contact structure and the adhesion layer of the further contact structure may include titanium tungsten.
According to various further embodiments of the semiconductor device the second metal layer of the contact structure and the second metal layer of the further contact structure may include copper.
According to various further embodiments of the semiconductor device the second metal layer may have a thickness of more than 5 micrometers.
According to various further embodiments the semiconductor device may further include a gate portion provided over the gate electrode of the semiconductor body between the contact structures_and electrically coupled to the gate electrode.
According to various further embodiments the semiconductor device may further include a dielectric material provided between the contact structures and covering the gate portion.
According to various further embodiments the semiconductor device may further include passivation material provided over the dielectric material between the contact structures. The passivation material may be also provided over portions of the contact structures.
According to various further embodiments of the semiconductor device the upper surfaces of the second metal layer of the contact structure and of the second metal layer of the further contact structure may be level.
According to various further embodiments of the semiconductor device the passivation material may be provided over the contact structures thereby encapsulating the contact structures.
According to various further embodiments the semiconductor device may further include an opening provided in the passivation material over the upper surface of each of the contact structures exposing the upper surface of each of the contact structures.
According to various further embodiments the semiconductor device may further include a further gate portion provided over the semiconductor body and electrically coupled to the gate portion, the further gate portion being covered by a dielectric material.
According to various further embodiments the semiconductor device may further include a gate contact structure provided over semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer, wherein the first metal layer of the gate contact structure may be electrically coupled with the gate portion and the further gate portion.
According to various further embodiments the semiconductor device may further include a tungsten layer arranged between the first metal layer of each of the contact structures and the semiconductor body.
According to various further embodiments of the semiconductor device the tungsten layer may include interconnections to connect a sensor for measuring at least one of temperature and current. The tungsten layer may be a fine pitch structured tungsten layer.
According to various further embodiments, the adhesion layer may be a reaction protection and adhesion layer.
In accordance with various further embodiments, a semiconductor device is provided which may include a semiconductor body including a first drift region, a second drift region and a gate electrode arranged between the drift regions; a first contact structure provided over the first drift region of the semiconductor body and having a first metal layer and a second metal layer over the first metal layer; a second contact structure provided over the second drift region of the semiconductor body and having a first metal layer and a second metal layer over the first metal layer, wherein the second contact structure may be laterally separated from the first contact structure.
According to various further embodiments the semiconductor device may further include an adhesion layer provided between the first metal layer and the second metal layer within each of the contact structures.
According to various further embodiments of the semiconductor device the first metal layer of the first contact structure and the first metal layer of the second contact structure may include aluminium.
According to various further embodiments of the semiconductor device the adhesion layer of the first contact structure and the adhesion layer of the second contact structure may include titanium tungsten.
According to various further embodiments of the semiconductor device the second metal layer of the first contact structure and the second metal layer of the second contact structure may include copper.
According to various further embodiments of the semiconductor device the second metal layer may have a thickness of more than 5 micrometers.
According to various further embodiments the semiconductor device may further include a gate portion provided over the gate electrode of the semiconductor body between the contact structures and electrically coupled to the gate electrode.
According to various further embodiments the semiconductor device may further include dielectric material provided between the contact structures and covering the gate portion.
According to various further embodiments the semiconductor device may further include passivation material provided over the dielectric material between the contact structures. The passivation material may be also provided over portions of the contact structures.
According to various further embodiments of the semiconductor device the upper surfaces of the second metal layer of the first contact structure and of the second metal layer of the second contact structure may be level.
According to various further embodiments of the semiconductor device the passivation material may be provided over the contact structures thereby encapsulating the contact structures.
According to various further embodiments the semiconductor device may further include an opening provided in the passivation material over the upper surface of each of the contact structures exposing the upper surface of each of the contact structures.
According to various further embodiments the semiconductor device may further include a further gate portion provided over the semiconductor body and electrically coupled to the gate portion, the further gate portion being covered by a dielectric material.
According to various further embodiments the semiconductor device may further include a further contact structure provided over semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer, wherein the first metal layer of the further contact structure may be electrically coupled with the gate portion and the further gate portion.
According to various further embodiments the semiconductor device may further include a tungsten layer arranged between the first metal layer of each of the contact structures and the semiconductor body.
According to various further embodiments of the semiconductor device the tungsten layer may include interconnections to connect a sensor for measuring at least one of temperature and current. The tungsten layer may be a fine pitch structured tungsten layer.
According to various further embodiments the semiconductor device may further include a backside metal layer provided on the backside of the semiconductor body.
According to various further embodiments of the semiconductor device the semiconductor device may be configured as a vertical transistor.
According to various further embodiments of the semiconductor device the backside metal layer may be configured as a drain terminal.
According to various further embodiments of the semiconductor device the first contact structure and the second contact structure may be configured as source terminals.
In accordance with various embodiments a method for manufacturing a semiconductor device is provided, wherein the method may include providing a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; depositing a first metal layer over the drift region of the semiconductor body; depositing an adhesion layer over the first metal layer; and depositing a second metal layer over the adhesion layer, wherein the stack comprising the first metal layer, the adhesion layer and the second metal layer may form a contact structure.
In accordance with various further embodiments a method for manufacturing a semiconductor device is provided, wherein the method may include providing a semiconductor body including a first drift region, a second drift region and a gate electrode arranged between the drift regions; depositing a first metal layer over the semiconductor body; depositing a second metal layer over the first metal layer; removing a portion of the first metal layer and a portion of the second metal layer in a region between the first drift region and the second drift region, such that a first contact structure is formed over the first drift region and a second contact structure is formed over the second drift region, wherein the first contact structure and the second contact structure are laterally separate from one another and each include a portion of the second metal layer arranged over a portion of the first metal layer.
While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.