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Artur Balasinski
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Cupertino, CA, US
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last 30 patents
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Patent Grant
Integrated scheme for semiconductor device verification
Patent number
6,681,376
Issue date
Jan 20, 2004
Cypress Semiconductor Corporation
Artur Balasinski
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Integrated scheme for predicting yield of semiconductor (MOS) devic...
Patent number
6,562,638
Issue date
May 13, 2003
Cypress Semiconductor Corp.
Artur Balasinski
H01 - BASIC ELECTRIC ELEMENTS