Ashish Kumar Goel

Person

Varanasi, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Method and device for configuration of PLDS
- Patent number RE43081
- Issue date Jan 10, 2012
- Sicronic Remote KG, LLC
- Ashish Kumar Goel
- 326 - Electronic digital logic circuitry
Information Patent Grant
Processing configuration data frames
- Patent number 7,774,682
- Issue date Aug 10, 2010
- Ashish Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic devices
- Patent number 7,606,969
- Issue date Oct 20, 2009
- Davinder Aggarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Rapid interconnect and logic testing of FPGA device
- Patent number 7,477,070
- Issue date Jan 13, 2009
- Sicronic Remote KG, LLC
- Pramod Kumar Singh
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus of reloading erroneous configuration data fram...
- Patent number 7,350,134
- Issue date Mar 25, 2008
- Sicronic Remote KG, LLC
- Ashish Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA-based digital circuit for reducing readback time
- Patent number 7,271,616
- Issue date Sep 18, 2007
- STMicroelectronics Pvt. Ltd.
- Ashish Kumar Goel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Rapid partial configuration of reconfigurable devices
- Patent number 7,206,919
- Issue date Apr 17, 2007
- STMicroelectronics Pvt. Ltd.
- Ashish Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and device for configuration of PLDs
- Patent number 7,157,935
- Issue date Jan 2, 2007
- STMicroelectronics Pvt. Ltd.
- Ashish K. Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoder scheme for making large size decoder
- Patent number 6,794,906
- Issue date Sep 21, 2004
- STMicroelectronics Pvt. Ltd.
- Ashish Kumar Goel
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
FPGA device and method for rapid interconnect and logic testing of...
- Publication number 20060255833
- Publication date Nov 16, 2006
- STMicroelectronics Pvt. Ltd.
- Pramod Kumar Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FPGA-based digital circuit for reducing readback time
- Publication number 20060022700
- Publication date Feb 2, 2006
- Ashish Kumar Goel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic devices
- Publication number 20050172070
- Publication date Aug 4, 2005
- STMicroelectronics Pvt. Ltd.
- Davinder Aggarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and device for configuration of PLDs
- Publication number 20050127943
- Publication date Jun 16, 2005
- STMicroelectronics Pvt. Ltd.
- Ashish K. Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus of reloading erroneous configuration data fram...
- Publication number 20040153923
- Publication date Aug 5, 2004
- STMicroelectronics Pvt, Ltd.
- Ashish Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Decoder scheme for making large size decoder
- Publication number 20040070424
- Publication date Apr 15, 2004
- Ashish Kumar Goel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Rapid partial configuration of reconfigurable devices
- Publication number 20030145193
- Publication date Jul 31, 2003
- STMicroelectronics Pvt. Ltd.
- Ashish Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING

Ashish Kumar Goel

Person

Patents Grantslast 30 patents

Method and device for configuration of PLDS

Processing configuration data frames

Programmable logic devices

Rapid interconnect and logic testing of FPGA device

Method and apparatus of reloading erroneous configuration data fram...

FPGA-based digital circuit for reducing readback time

Rapid partial configuration of reconfigurable devices

Method and device for configuration of PLDs

Decoder scheme for making large size decoder

Patents Applicationslast 30 patents

FPGA device and method for rapid interconnect and logic testing of...

FPGA-based digital circuit for reducing readback time

Programmable logic devices

Method and device for configuration of PLDs

Method and apparatus of reloading erroneous configuration data fram...

Decoder scheme for making large size decoder

Rapid partial configuration of reconfigurable devices