Ashish Pancholy

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Eye-safe laser navigation sensor
- Patent number 7,809,035
- Issue date Oct 5, 2010
- Cypress Semiconductor Corporation
- Steven Sanders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MRAM data line configuration and method of operation
- Patent number 6,862,215
- Issue date Mar 1, 2005
- Silicon Magnetic Systems
- Ashish Pancholy
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit with selective address path
- Patent number 6,775,191
- Issue date Aug 10, 2004
- Silicon Magnetic Systems
- Ashish Pancholy
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetic memory cell and method for assigning tunable writing currents
- Patent number 6,683,815
- Issue date Jan 27, 2004
- Silicon Magnetic Systems
- Eugene Y. Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level programmable voltage control and output buffer with sel...
- Patent number 6,664,810
- Issue date Dec 16, 2003
- Cypress Semiconductor Corporation
- Ashish Pancholy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Localized MRAM data line and method of operation
- Patent number 6,639,831
- Issue date Oct 28, 2003
- Silicon Magnetic Systems
- Ashish Pancholy
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory having independent read port and write port an...
- Patent number 6,445,645
- Issue date Sep 3, 2002
- Cypress Semiconductor Corporation
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Grant
Direct bit line-bit line defect detection test mode for SRAM
- Patent number 6,388,927
- Issue date May 14, 2002
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory having a read/write address bus and process fo...
- Patent number 6,385,128
- Issue date May 7, 2002
- Cypress Semiconductor Corp.
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level programmable voltage control and output buffer with sel...
- Patent number 6,380,762
- Issue date Apr 30, 2002
- Cypress Semiconductor Corporation
- Ashish Pancholy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus to prevent latch-up in CMOS devices
- Patent number 6,359,316
- Issue date Mar 19, 2002
- Cypress Semiconductor Corp.
- Peter H. Voss
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit and method for implementing single-cycle read/write operati...
- Patent number 6,292,403
- Issue date Sep 18, 2001
- Cypress Semiconductor Corp.
- Ashish Pancholy
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan path circuitry including a programmable delay circuit
- Patent number 6,286,118
- Issue date Sep 4, 2001
- Cypress Semiconductor Corporation
- Jonathan F. Churchill
- G01 - MEASURING TESTING
Information Patent Grant
Random access memory having independent read port and write port an...
- Patent number 6,262,936
- Issue date Jul 17, 2001
- Cypress Semiconductor Corp.
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous random access memory having a read/write address bus an...
- Patent number 6,262,937
- Issue date Jul 17, 2001
- Cypress Semiconductor Corp.
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan path circuitry for programming a variable clock pulse width
- Patent number 6,115,836
- Issue date Sep 5, 2000
- Cypress Semiconductor Corporation
- Jonathan F. Churchill
- G01 - MEASURING TESTING
Information Patent Grant
Circuit and method for implementing single-cycle read/write operati...
- Patent number 6,069,839
- Issue date May 30, 2000
- Cypress Semiconductor Corp.
- Ashish Pancholy
- G11 - INFORMATION STORAGE
Information Patent Grant
Test mode features for synchronous pipelined memories
- Patent number 6,006,347
- Issue date Dec 21, 1999
- Cypress Semiconductor Corporation
- Jonathan F. Churchill
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan path circuitry including an output register having a flow thro...
- Patent number 5,953,285
- Issue date Sep 14, 1999
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan path circuitry including a programmable delay circuit
- Patent number 5,936,977
- Issue date Aug 10, 1999
- Cypress Semiconductor Corp.
- Jonathan F. Churchill
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for reducing skew among input signals within a...
- Patent number 5,903,174
- Issue date May 11, 1999
- Cypress Semiconductor Corp.
- Greg J. Landry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for self-resetting logic circuitry
- Patent number 5,864,251
- Issue date Jan 26, 1999
- Cypress Semiconductor Corporation
- Raymond E. Bloker
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Eye-safe laser navigation sensor
- Publication number 20070230525
- Publication date Oct 4, 2007
- Steven Sanders
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RANDOM ACCESS MEMORY HAVING A READ/WRITE ADDRESS BUS AND PROCESS FO...
- Publication number 20020054535
- Publication date May 9, 2002
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE
Information Patent Application
Random access memory having independent read port and write port an...
- Publication number 20010043506
- Publication date Nov 22, 2001
- Mathew R. Arcoleo
- G11 - INFORMATION STORAGE

Ashish Pancholy

Person

Patents Grantslast 30 patents

Eye-safe laser navigation sensor

MRAM data line configuration and method of operation

Memory circuit with selective address path

Magnetic memory cell and method for assigning tunable writing currents

Multi-level programmable voltage control and output buffer with sel...

Localized MRAM data line and method of operation

Random access memory having independent read port and write port an...

Direct bit line-bit line defect detection test mode for SRAM

Random access memory having a read/write address bus and process fo...

Multi-level programmable voltage control and output buffer with sel...

Method and apparatus to prevent latch-up in CMOS devices

Circuit and method for implementing single-cycle read/write operati...

Scan path circuitry including a programmable delay circuit

Random access memory having independent read port and write port an...

Synchronous random access memory having a read/write address bus an...

Scan path circuitry for programming a variable clock pulse width

Circuit and method for implementing single-cycle read/write operati...

Test mode features for synchronous pipelined memories

Scan path circuitry including an output register having a flow thro...

Scan path circuitry including a programmable delay circuit

Method and apparatus for reducing skew among input signals within a...

Method and apparatus for self-resetting logic circuitry

Patents Applicationslast 30 patents

Eye-safe laser navigation sensor

RANDOM ACCESS MEMORY HAVING A READ/WRITE ADDRESS BUS AND PROCESS FO...

Random access memory having independent read port and write port an...