Ashot Melik-Martirosian

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory device having trapezoidal bitlines and method of fabricating...
- Patent number 8,957,472
- Issue date Feb 17, 2015
- Spansion LLC
- Ashot Melik-Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory devices and methods for fabricating same
- Patent number 8,748,972
- Issue date Jun 10, 2014
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory devices and methods for fabricating the same
- Patent number 8,486,782
- Issue date Jul 16, 2013
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device having trapezoidal bitlines and method of fabricating...
- Patent number 8,125,018
- Issue date Feb 28, 2012
- Spansion LLC
- Ashot Melik-Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory comprising dual charge storage nodes and metho...
- Patent number 8,076,712
- Issue date Dec 13, 2011
- Spansion LLC
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-bit memory device having isolation material disposed underneat...
- Patent number 8,076,715
- Issue date Dec 13, 2011
- Spansion LLC
- Ashot Melik-Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory programming and verification with reduced leakage current
- Patent number 8,031,528
- Issue date Oct 4, 2011
- Spansion LLC
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for adaptive memory cell overerase compensation
- Patent number 7,929,353
- Issue date Apr 19, 2011
- Spansion LLC
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory comprising dual charge storage nodes and metho...
- Patent number 7,767,517
- Issue date Aug 3, 2010
- Spansion LLC
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programming in memory devices using source bitline voltage bias
- Patent number 7,746,698
- Issue date Jun 29, 2010
- Spansion LLC
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for fabricating flash memory devices
- Patent number 7,696,038
- Issue date Apr 13, 2010
- Spansion LLC
- Ning Cheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell dual pocket implant
- Patent number 7,678,674
- Issue date Mar 16, 2010
- Spansion LLC
- Shankar Sinha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating a split charge storage node semiconductor m...
- Patent number 7,666,739
- Issue date Feb 23, 2010
- Spansion LLC
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Work function engineering for FN erase of a memory device with mult...
- Patent number 7,659,569
- Issue date Feb 9, 2010
- Spansion LLC
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for fabricating a memory device including a dual bit memory...
- Patent number 7,635,627
- Issue date Dec 22, 2009
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory programming and verification with reduced leakage current
- Patent number 7,630,253
- Issue date Dec 8, 2009
- Spansion LLC
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-phase wordline erasing for flash memory
- Patent number 7,626,869
- Issue date Dec 1, 2009
- Spansion LLC
- Xuguang Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for adaptive memory cell overerase compensation
- Patent number 7,619,934
- Issue date Nov 17, 2009
- Spansion LLC
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and methods for its fabrication
- Patent number 7,564,091
- Issue date Jul 21, 2009
- Spansion LLC
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Select transistor using buried bit line from core
- Patent number 7,561,457
- Issue date Jul 14, 2009
- Spansion LLC
- Mark Randolph
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of increasing erase speed in memory arrays
- Patent number 7,462,907
- Issue date Dec 9, 2008
- Spansion LLC
- Ashot Melik-Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory array tester information processing system
- Patent number 7,443,746
- Issue date Oct 28, 2008
- Spansion LLC
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and methods for its fabrication
- Patent number 7,432,156
- Issue date Oct 7, 2008
- Spansion LLC
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell having combination raised source and drain and method o...
- Patent number 7,414,277
- Issue date Aug 19, 2008
- Spansion, LLC
- Ashot Melik-Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pocket implant for complementary bit disturb improvement and chargi...
- Patent number 6,958,272
- Issue date Oct 25, 2005
- Advanced Micro Devices, Inc.
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual cell memory device having a top dielectric stack
- Patent number 6,894,932
- Issue date May 17, 2005
- Advanced Micro Devices, Inc.
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with reduced operating voltage having dielectric stack
- Patent number 6,868,014
- Issue date Mar 15, 2005
- Advanced Micro Devices, Inc.
- Ashot Melik-Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device having a thin top dielectric and method of erasing same
- Patent number 6,862,221
- Issue date Mar 1, 2005
- Advanced Micro Devices, Inc.
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory device having four-bit cells
- Patent number 6,735,124
- Issue date May 11, 2004
- Advanced Micro Devices, Inc.
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
FLASH MEMORY DEVICES AND METHODS FOR FABRICATING SAME
- Publication number 20130277733
- Publication date Oct 24, 2013
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD FO FABRICATING...
- Publication number 20120122285
- Publication date May 17, 2012
- Ashot Melik-Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...
- Publication number 20100283100
- Publication date Nov 11, 2010
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT
- Publication number 20100027350
- Publication date Feb 4, 2010
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR ADAPTIVE MEMORY CELL OVERERASE COMPENSATION
- Publication number 20100020607
- Publication date Jan 28, 2010
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS
- Publication number 20090154246
- Publication date Jun 18, 2009
- SPANSION LLC
- Zhizheng Liu
- G11 - INFORMATION STORAGE
Information Patent Application
WORK FUNCTION ENGINEERING FOR FN ERAS OF A MEMORY DEVICE WITH MULTI...
- Publication number 20090146201
- Publication date Jun 11, 2009
- SPANSION LLC
- Wei Zheng
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHODS FOR ITS FABRICATION
- Publication number 20080315290
- Publication date Dec 25, 2008
- Chungho LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY
- Publication number 20080279014
- Publication date Nov 13, 2008
- SPANSION LLC
- Xuguang Wang
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-BIT MEMORY DEVICE HAVING ISOLATION MATERIAL DISPOSED UNDERNEAT...
- Publication number 20080157263
- Publication date Jul 3, 2008
- Ashot Melik-Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING A SPLIT CHARGE STORAGE NODE SEMICONDUCTOR M...
- Publication number 20080153222
- Publication date Jun 26, 2008
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING A MEMORY DEVICE INCLUDING A DUAL BIT MEMORY...
- Publication number 20080153228
- Publication date Jun 26, 2008
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...
- Publication number 20080149999
- Publication date Jun 26, 2008
- Chungho Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR ADAPTIVE MEMORY CELL OVERERASE COMPENSATION
- Publication number 20080151619
- Publication date Jun 26, 2008
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Application
FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
- Publication number 20080149989
- Publication date Jun 26, 2008
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECT TRANSISTOR USING BURIED BIT LINE FROM CORE
- Publication number 20080123384
- Publication date May 29, 2008
- SPANSION LLC
- Mark RANDOLPH
- G11 - INFORMATION STORAGE
Information Patent Application
Flash memory programming and verification with reduced leakage current
- Publication number 20070237003
- Publication date Oct 11, 2007
- Ashot Melik-Martirosian
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device having trapezoidal bitlines and method of fabricating...
- Publication number 20060151821
- Publication date Jul 13, 2006
- Ashot Melik-Martirosian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pocket implant for complementary bit disturb improvement and chargi...
- Publication number 20050153508
- Publication date Jul 14, 2005
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS

Ashot Melik-Martirosian

Person

Patents Grantslast 30 patents

Memory device having trapezoidal bitlines and method of fabricating...

Flash memory devices and methods for fabricating same

Flash memory devices and methods for fabricating the same

Memory device having trapezoidal bitlines and method of fabricating...

Semiconductor memory comprising dual charge storage nodes and metho...

Dual-bit memory device having isolation material disposed underneat...

Flash memory programming and verification with reduced leakage current

Method and apparatus for adaptive memory cell overerase compensation

Semiconductor memory comprising dual charge storage nodes and metho...

Programming in memory devices using source bitline voltage bias

Methods for fabricating flash memory devices

Memory cell dual pocket implant

Methods for fabricating a split charge storage node semiconductor m...

Work function engineering for FN erase of a memory device with mult...

Methods for fabricating a memory device including a dual bit memory...

Flash memory programming and verification with reduced leakage current

Multi-phase wordline erasing for flash memory

Method and apparatus for adaptive memory cell overerase compensation

Memory device and methods for its fabrication

Select transistor using buried bit line from core

Method of increasing erase speed in memory arrays

Memory array tester information processing system

Memory device and methods for its fabrication

Memory cell having combination raised source and drain and method o...

Pocket implant for complementary bit disturb improvement and chargi...

Dual cell memory device having a top dielectric stack

Memory device with reduced operating voltage having dielectric stack

Memory device having a thin top dielectric and method of erasing same

Flash memory device having four-bit cells

Patents Applicationslast 30 patents

FLASH MEMORY DEVICES AND METHODS FOR FABRICATING SAME

MEMORY DEVICE HAVING TRAPEZOIDAL BITLINES AND METHOD FO FABRICATING...

SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...

FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT

METHOD AND APPARATUS FOR ADAPTIVE MEMORY CELL OVERERASE COMPENSATION

PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS

WORK FUNCTION ENGINEERING FOR FN ERAS OF A MEMORY DEVICE WITH MULTI...

MEMORY DEVICE AND METHODS FOR ITS FABRICATION

MULTI-PHASE WORDLINE ERASING FOR FLASH MEMORY

DUAL-BIT MEMORY DEVICE HAVING ISOLATION MATERIAL DISPOSED UNDERNEAT...

METHODS FOR FABRICATING A SPLIT CHARGE STORAGE NODE SEMICONDUCTOR M...

METHODS FOR FABRICATING A MEMORY DEVICE INCLUDING A DUAL BIT MEMORY...

SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHO...

METHOD AND APPARATUS FOR ADAPTIVE MEMORY CELL OVERERASE COMPENSATION

FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME

SELECT TRANSISTOR USING BURIED BIT LINE FROM CORE

Flash memory programming and verification with reduced leakage current

Memory device having trapezoidal bitlines and method of fabricating...

Pocket implant for complementary bit disturb improvement and chargi...