Ashutosh Ashutosh

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Hillsboro, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Methods of channel stress engineering and structures formed thereby
- Patent number 8,716,806
- Issue date May 6, 2014
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reliability of high-K gate dielectric layers
- Patent number 8,394,694
- Issue date Mar 12, 2013
- Intel Corporation
- Adrien R. Lavoie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of channel stress engineering and structures formed thereby
- Patent number 8,193,049
- Issue date Jun 5, 2012
- Intel Corporation
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Boundaries with elevated deuterium levels
- Patent number 7,842,983
- Issue date Nov 30, 2010
- Intel Corporation
- Ashutosh Ashutosh
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Reliability of high-K gate dielectric layers
- Publication number 20120286372
- Publication date Nov 15, 2012
- Adrien R. Lavoie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF CHANNEL STRESS ENGINEERING AND STRUCTURES FORMED THEREBY
- Publication number 20120211839
- Publication date Aug 23, 2012
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Drive current enhancement in tri-gate MOSFETS by introduction of co...
- Publication number 20110147804
- Publication date Jun 23, 2011
- Rishabh Mehandru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of channel stress engineering and structures formed thereby
- Publication number 20100148270
- Publication date Jun 17, 2010
- Oleg Golonzka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Boundaries with elevated deuterium levels
- Publication number 20090321855
- Publication date Dec 31, 2009
- Ashutosh Ashutosh
- H01 - BASIC ELECTRIC ELEMENTS