Patent Application
20110147804
Carbon-doped silicon epitaxial layers are deposited on source and drain areas of Tri-gate transistors to generate a tensile stress in the channel of transistor to enhance the carrier mobility and the drive current of the channel. This technique, though, only provides a relatively low carrier mobility and, consequently, has a relatively low saturated drain current Idsat and linear drain current Idlin.
Embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which:
It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.
Embodiments are described herein for enhancing drive current in Tri-gate MOSFETS by using Ion implantation to create compressive metal gate stress. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments disclosed herein. One skilled in the relevant art will recognize, however, that the embodiments disclosed herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the specification.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not to be construed as necessarily preferred or advantageous over other embodiments.
The subject matter disclosed herein provides a technique for further enhancing the carrier mobility and drive current by forming compressive metal gate stress by implantation of ions into the metal gate to generate out-of-plane compression in the channel of the transistor.
As critical dimensions of transistors become increasingly smaller with each new generation of transistors, the process for gate metal deposition tends to be a chemical vapor deposition (CVD) process, such as an atomic layer deposition (ALD) process, as opposed to sputtering in order to avoid formation of voids in the gate metal. It is known that such ALD-deposited metals have an intrinsic tensile strain instead of a compressive strain that is normally seen in connection with sputtered materials. The subject matter disclosed herein forms a compressive stress in an ALD-deposited gate metal layer by implanting ions, such as, but not limited to, nitrogen, xenon, argon, neon, krypton, radon, ef-carbon, aluminum or titanium, or combinations thereof, in the metal gate.
The subject matter disclosed herein relates to using ion implantation to form compressive metal-gate stress in Tri-gate, or finFET, NMOS transistors and to thereby generate out-of-plane compression in the channel of the transistor, which enhances carrier mobility and drive current of the channel. The compressive gate strain formed by the ion implantation transfers to the channel as compressive strain end of line for the dominate sidewall transistor of the Tri-gate transistor. According to one exemplary embodiment, carrier mobility and drive current are significantly enhanced by exerting out-of-plane compression on a channel that is oriented in the <110> direction that is formed on a wafer having a top surface (110) crystalline lattice, in which the sidewall of the channel has a (100) crystalline lattice orientation. Similar carrier mobility and drive current enhancement from out-of-plane compression is also exhibited for a channel oriented in a <100> direction that is formed on a wafer having a top surface (100) crystalline lattice, in which the sidewall of the channel has a (100) orientation.
According to the subject matter disclosed herein, ions are implanted in the metal gate of a Tri-gate NMOS transistor to generate compressive stress in a channel that is oriented in the <110> direction and is formed on the top surface of a wafer having a (100) crystalline lattice orientation. Alternatively, compressive stress can be generated in a channel by ion implantation into the metal gate of a Tri-gate transistor such that the channel is oriented in the <100> direction that has been formed on the top surface of a wafer having a (100) crystalline lattice orientation. The techniques of the subject matter disclosed herein may be less complicated that conventional EPI growth techniques that form channel strain, which requires multiple steps. Additionally, as the pitch and gate scales, EPI regions used by conventional techniques shrink much faster than gate (or channel length Lg), which makes the techniques disclosed herein attractive at narrower pitches.
Tri-gate transistor 200 in which fin 201 and gate metal film 202 are shown. Fin 201 is disposed between oxides 203. As depicted in
During the second stage of the process after the ion implantation step 102, flow continues to step 103 where the gate fill 205, such as a low-resistance metal, is completed by using a well-known ALD process and followed by polishing.
In another exemplary embodiment, the ion implantation of step 103 could be done after the gate fill and polish of step 104.
According to the subject matter disclosed herein, a similar benefit for long-channel devices is also seen for a <100> channel orientation on (100) top wafer, which also has a <100> oriented channel on (100) sidewall. If either a (110) top surface with a <110> channel orientation or a (100) top surface with a <100> channel orientation is used, about a 37% Idsat gain and about a 17% Idlin gain was observed in simulations.
The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of this description, as those skilled in the relevant art will recognize.
These modifications can be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the scope to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the embodiments disclosed herein is to be determined by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
